diff options
author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-02-13 14:01:57 +0000 |
---|---|---|
committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-02-20 13:30:02 +0000 |
commit | 73dcf05f633b5e3a7d9a16338a64c1832ef38388 (patch) | |
tree | b66442229292c0b699e5ae7f6c1b236648c21a87 /src/arch/arm/isa/insts | |
parent | 26b03914d7dbcf6b6c8c0a9c08d4e3ff81365376 (diff) | |
download | gem5-73dcf05f633b5e3a7d9a16338a64c1832ef38388.tar.xz |
arch-arm: Add AArch32 HLT Semihosting interface
AArch32 HLT instruction is now able to issue Arm Semihosting commands as
the AArch64 counterpart in either Arm and Thumb mode.
Change-Id: I77da73d2e6a9288c704a5f646f4447022517ceb6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8372
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/insts')
-rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 566ea4b9d..a183f5d0a 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -62,6 +62,31 @@ let {{ decoder_output = SemihostConstructor.subst(svcIop) exec_output = PredOpExecute.subst(svcIop) + hltCode = ''' + ThreadContext *tc = xc->tcBase(); + + const auto semihost_imm = Thumb? 0x3C : 0xF000; + + if (ArmSystem::haveSemihosting(tc) && imm == semihost_imm) { + R0 = ArmSystem::callSemihosting32(tc, R0, R1); + } else { + // HLT instructions aren't implemented, so treat them as undefined + // instructions. + fault = std::make_shared<UndefinedInstruction>( + machInst, false, mnemonic); + } + ''' + + hltIop = InstObjParams("hlt", "Hlt", "ImmOp", + { "code": hltCode, + "predicate_test": predicateTest, + "thumb_semihost": '0x3C', + "arm_semihost": '0xF000' }, + ["IsNonSpeculative"]) + header_output += ImmOpDeclare.subst(hltIop) + decoder_output += SemihostConstructor.subst(hltIop) + exec_output += PredOpExecute.subst(hltIop) + smcCode = ''' HCR hcr = Hcr; CPSR cpsr = Cpsr; |