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author | Gabe Black <gblack@eecs.umich.edu> | 2012-01-07 02:15:35 -0800 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2012-01-07 02:15:35 -0800 |
commit | ec936364b7238cddea7734ea79c6e04b52a683c6 (patch) | |
tree | 788fc19c3ba599d6f39d3990769888a0650be5ff /src/arch/arm/isa/insts | |
parent | 36a822f08e88483b41af214ace4fd3dccf3aa8cb (diff) | |
parent | 9b52717a92ed9592bd98a41683509f538262a5c7 (diff) | |
download | gem5-ec936364b7238cddea7734ea79c6e04b52a683c6.tar.xz |
Merge with the main repository again.
Diffstat (limited to 'src/arch/arm/isa/insts')
-rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 495cb722c..b671843cf 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -49,7 +49,8 @@ let {{ svcIop = InstObjParams("svc", "Svc", "PredOp", { "code": svcCode, - "predicate_test": predicateTest }, ["IsSyscall"]) + "predicate_test": predicateTest }, + ["IsSyscall", "IsNonSpeculative", "IsSerializeAfter"]) header_output = BasicDeclare.subst(svcIop) decoder_output = BasicConstructor.subst(svcIop) exec_output = PredOpExecute.subst(svcIop) |