summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa/insts
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:15 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:15 -0500
commit2d08b8de9166552a3214012ecdfb98bd8fd3eafb (patch)
tree612c5e35345bbd2e28e084abbc5ece3d1a236deb /src/arch/arm/isa/insts
parent57c4d37c102e2fb4d1c86fe1d583ee67c76945b1 (diff)
downloadgem5-2d08b8de9166552a3214012ecdfb98bd8fd3eafb.tar.xz
ARM: Implement the version of VMRS that writes to the APSR.
Diffstat (limited to 'src/arch/arm/isa/insts')
-rw-r--r--src/arch/arm/isa/insts/fp.isa8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index 0abae6a20..c5ce813f9 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -205,6 +205,14 @@ let {{
decoder_output += VfpRegRegOpConstructor.subst(vmrsIop);
exec_output += PredOpExecute.subst(vmrsIop);
+ vmrsApsrCode = "Dest = (MiscOp1 & imm) | (Dest & ~imm);"
+ vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "VfpRegRegImmOp",
+ { "code": vmrsApsrCode,
+ "predicate_test": predicateTest }, [])
+ header_output += VfpRegRegImmOpDeclare.subst(vmrsApsrIop);
+ decoder_output += VfpRegRegImmOpConstructor.subst(vmrsApsrIop);
+ exec_output += PredOpExecute.subst(vmrsApsrIop);
+
vmovImmSCode = '''
FpDest.uw = bits(imm, 31, 0);
'''