diff options
author | Andreas Sandberg <andreas.sandberg@arm.com> | 2018-02-08 20:13:13 +0000 |
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committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2018-02-19 14:24:46 +0000 |
commit | 6039da55d87fb27b149ac3da0ebce41bb55a3bee (patch) | |
tree | 0accdc76afa3790eb04d878d89e5f5158fd25572 /src/arch/arm/isa/insts | |
parent | 80427ea030b521779521f57b092bc6b4afc86ab2 (diff) | |
download | gem5-6039da55d87fb27b149ac3da0ebce41bb55a3bee.tar.xz |
arch-arm: Add aarch64 semihosting support
Add basic support for Arm Semihosting 2.0 simulation calls [1]. These
calls let the guest system call a simulator or debugger to request
OS-like support when running bare metal code.
With the exception of SYS_SYSTEM, this implementation supports all of
the Semihosting 2.0 specification in aarch64.
[1] https://developer.arm.com/docs/100863/latest/preface
Change-Id: I08c153c18a4a4fb9f95d318e2a029724935192a7
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8147
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src/arch/arm/isa/insts')
-rw-r--r-- | src/arch/arm/isa/insts/misc64.isa | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/misc64.isa b/src/arch/arm/isa/insts/misc64.isa index 2483b75b0..faac5cfcf 100644 --- a/src/arch/arm/isa/insts/misc64.isa +++ b/src/arch/arm/isa/insts/misc64.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2011-2013, 2016-2017 ARM Limited +// Copyright (c) 2011-2013, 2016-2018 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -174,4 +174,23 @@ let {{ header_output += BasicDeclare.subst(brkIop) decoder_output += BasicConstructor64.subst(brkIop) exec_output += BasicExecute.subst(brkIop) + + hltCode = ''' + ThreadContext *tc = xc->tcBase(); + if (ArmSystem::haveSemihosting(tc) && bits(machInst, 20, 5) == 0xF000) { + X0 = ArmSystem::callSemihosting64(tc, X0 & mask(32), X1); + } else { + // HLT instructions aren't implemented, so treat them as undefined + // instructions. + fault = std::make_shared<UndefinedInstruction>( + machInst, false, mnemonic); + } + + ''' + + hltIop = InstObjParams("hlt", "Hlt64", "ArmStaticInst", + hltCode, ["IsNonSpeculative"]) + header_output += BasicDeclare.subst(hltIop) + decoder_output += BasicConstructor64.subst(hltIop) + exec_output += BasicExecute.subst(hltIop) }}; |