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author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:05 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:05 -0500 |
commit | cbdebf852efd56651a18532c6ffbe7ac580aa539 (patch) | |
tree | b54a69ff77cb04a876835f6033a3635d495aa458 /src/arch/arm/isa/insts | |
parent | caa95639ec2fe7cd45edf679d5fbf6b7a7072fb3 (diff) | |
download | gem5-cbdebf852efd56651a18532c6ffbe7ac580aa539.tar.xz |
ARM: Implement SVC (was SWI) outside of the decoder.
Diffstat (limited to 'src/arch/arm/isa/insts')
-rw-r--r-- | src/arch/arm/isa/insts/insts.isa | 3 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 57 |
2 files changed, 60 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/insts.isa b/src/arch/arm/isa/insts/insts.isa index 2e94a43c9..04dc867c7 100644 --- a/src/arch/arm/isa/insts/insts.isa +++ b/src/arch/arm/isa/insts/insts.isa @@ -46,6 +46,9 @@ //Loads of a single item ##include "ldr.isa" +//Miscellaneous instructions that don't fit elsewhere +##include "misc.isa" + //Stores of a single item ##include "str.isa" diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa new file mode 100644 index 000000000..df5fa2ad7 --- /dev/null +++ b/src/arch/arm/isa/insts/misc.isa @@ -0,0 +1,57 @@ +// -*- mode:c++ -*- + +// Copyright (c) 2010 ARM Limited +// All rights reserved +// +// The license below extends only to copyright in the software and shall +// not be construed as granting a license to any other intellectual +// property including but not limited to intellectual property relating +// to a hardware implementation of the functionality of the software +// licensed hereunder. You may use the software subject to the license +// terms below provided that you ensure that this notice is replicated +// unmodified and in its entirety in all distributions of the software, +// modified or unmodified, in source code or in binary form. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Gabe Black + +let {{ + + svcCode = ''' +#if FULL_SYSTEM + fault = new SupervisorCall; +#else + fault = new SupervisorCall(machInst); +#endif + ''' + + svcIop = InstObjParams("svc", "Svc", "PredOp", + { "code": svcCode, + "predicate_test": predicateTest }, ["IsSyscall"]) + header_output = BasicDeclare.subst(svcIop) + decoder_output = BasicConstructor.subst(svcIop) + exec_output = PredOpExecute.subst(svcIop) + +}}; |