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author | Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> | 2017-04-05 13:24:23 -0500 |
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committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
commit | 166da650a3c864b31193ade893ed99e547c67644 (patch) | |
tree | 84236bf28007885e864e885fab8e715e332affa6 /src/arch/arm/isa/insts | |
parent | 00da08902918da13fccc3f2266b7b2f5d0080708 (diff) | |
download | gem5-166da650a3c864b31193ade893ed99e547c67644.tar.xz |
arch: ISA parser additions of vector registers
Reiley's update :) of the isa parser definitions. My addition of the
vector element operand concept for the ISA parser. Nathanael's modification
creating a hierarchy between vector registers and its constituencies to the
isa parser.
Some fixes/updates on top to consider instructions as vectors instead of
floating when they use the VectorRF. Some counters added to all the
models to keep faithful counts.
Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2706
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/insts')
-rw-r--r-- | src/arch/arm/isa/insts/fp64.isa | 8 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/neon64.isa | 24 |
2 files changed, 22 insertions, 10 deletions
diff --git a/src/arch/arm/isa/insts/fp64.isa b/src/arch/arm/isa/insts/fp64.isa index 706f77fb0..a5e1085de 100644 --- a/src/arch/arm/isa/insts/fp64.isa +++ b/src/arch/arm/isa/insts/fp64.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2012-2013 ARM Limited +// Copyright (c) 2012-2013, 2016 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -123,9 +123,11 @@ let {{ exec_output += BasicExecute.subst(fmovCoreRegXIop); fmovUCoreRegXCode = vfp64EnabledCheckCode + ''' + /* Explicitly merge with previous value */ + AA64FpDestP0_uw = AA64FpDestP0_uw; + AA64FpDestP1_uw = AA64FpDestP1_uw; AA64FpDestP2_uw = XOp1_ud; - AA64FpDestP3_uw = XOp1_ud >> 32; - ''' + AA64FpDestP3_uw = XOp1_ud >> 32;''' fmovUCoreRegXIop = InstObjParams("fmov", "FmovUCoreRegX", "FpRegRegOp", { "code": fmovUCoreRegXCode, "op_class": "FloatMiscOp" }, []) diff --git a/src/arch/arm/isa/insts/neon64.isa b/src/arch/arm/isa/insts/neon64.isa index 7c9040be3..4897e7c91 100644 --- a/src/arch/arm/isa/insts/neon64.isa +++ b/src/arch/arm/isa/insts/neon64.isa @@ -1,6 +1,6 @@ // -*- mode: c++ -*- -// Copyright (c) 2012-2013, 2015 ARM Limited +// Copyright (c) 2012-2013, 2015-2016 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -225,11 +225,16 @@ let {{ AA64FpDestP%(destReg)d_uw = gtoh(destReg.regs[%(reg)d]); ''' % { "reg" : reg, "destReg": destReg } destReg += 1 - if destCnt < 4 and not hi: # zero upper half - for reg in range(destCnt, 4): - eWalkCode += ''' - AA64FpDestP%(reg)d_uw = 0; - ''' % { "reg" : reg } + if destCnt < 4: + if hi: # Explicitly merge with lower half + for reg in range(0, destCnt): + eWalkCode += ''' + AA64FpDestP%(reg)d_uw = AA64FpDestP%(reg)d_uw;''' % { "reg" : reg } + else: # zero upper half + for reg in range(destCnt, 4): + eWalkCode += ''' + AA64FpDestP%(reg)d_uw = 0;''' % { "reg" : reg } + iop = InstObjParams(name, Name, "DataX2RegImmOp" if byElem else "DataX2RegOp", { "code": eWalkCode, @@ -429,11 +434,16 @@ let {{ AA64FpDestP%(destReg)d_uw = gtoh(destReg.regs[%(reg)d]); ''' % { "reg" : reg, "destReg": destReg } destReg += 1 - if not hi: + if hi: + for reg in range(0, 2): # Explicitly merge with the lower half + eWalkCode += ''' + AA64FpDestP%(reg)d_uw = AA64FpDestP%(reg)d_uw;''' % { "reg" : reg } + else: for reg in range(2, 4): # zero upper half eWalkCode += ''' AA64FpDestP%(reg)d_uw = 0; ''' % { "reg" : reg } + iop = InstObjParams(name, Name, "DataX1RegImmOp" if hasImm else "DataX1RegOp", { "code": eWalkCode, |