diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-02-23 15:10:49 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-02-23 15:10:49 -0600 |
| commit | 326191adc9ed16c672a7f2442055dc8a23626739 (patch) | |
| tree | 0fd6c32aea92f63d36b1d36b82cae145b748afc1 /src/arch/arm/isa/insts | |
| parent | bb319a589e72c006269d6f82fdfa715cc3a6caaf (diff) | |
| download | gem5-326191adc9ed16c672a7f2442055dc8a23626739.tar.xz | |
ARM: Squash state on FPSCR stride or len write.
Diffstat (limited to 'src/arch/arm/isa/insts')
| -rw-r--r-- | src/arch/arm/isa/insts/fp.isa | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa index 961b9a355..4911d50f1 100644 --- a/src/arch/arm/isa/insts/fp.isa +++ b/src/arch/arm/isa/insts/fp.isa @@ -209,7 +209,8 @@ let {{ { "code": vmsrFpscrCode, "predicate_test": predicateTest, "op_class": "SimdFloatMiscOp" }, - ["IsSerializeAfter","IsNonSpeculative"]) + ["IsSerializeAfter","IsNonSpeculative", + "IsSquashAfter"]) header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop); decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop); exec_output += PredOpExecute.subst(vmsrFpscrIop); |