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| author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-07-12 13:49:24 +0100 |
|---|---|---|
| committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-10-13 08:41:08 +0000 |
| commit | 6b41bea7447316cb45dc2063f512dd046e22c598 (patch) | |
| tree | 9d5d986c27aa69c112cd104be7ded252561b2800 /src/arch/arm/isa/insts | |
| parent | b10a0092aecbc6927e9a2336188615ed97614fd0 (diff) | |
| download | gem5-6b41bea7447316cb45dc2063f512dd046e22c598.tar.xz | |
arch-arm: Signal an event when executing store exclusives
When a store exclusive is executed, whether it is successful or not,
the exclusives monitor is cleared and therefore we need to signal an
event for the PE.
Change-Id: I383c88c769c0ac5f5d36c4b5d39c9681134d3a20
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4480
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/insts')
| -rw-r--r-- | src/arch/arm/isa/insts/str.isa | 8 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/str64.isa | 8 |
2 files changed, 10 insertions, 6 deletions
diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa index 3f595692a..1c697d3ff 100644 --- a/src/arch/arm/isa/insts/str.isa +++ b/src/arch/arm/isa/insts/str.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010-2011 ARM Limited +// Copyright (c) 2010-2011,2017 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -228,7 +228,8 @@ let {{ def __init__(self, *args, **kargs): super(StoreImmEx, self).__init__(*args, **kargs) - self.codeBlobs["postacc_code"] = "Result = !writeResult;" + self.codeBlobs["postacc_code"] = \ + "Result = !writeResult; SevMailbox = 1; LLSCLock = 0;" class StoreImm(StoreImmInst, StoreSingle): decConstBase = 'LoadStoreImm' @@ -307,7 +308,8 @@ let {{ def __init__(self, *args, **kargs): super(StoreDoubleImmEx, self).__init__(*args, **kargs) - self.codeBlobs["postacc_code"] = "Result = !writeResult;" + self.codeBlobs["postacc_code"] = \ + "Result = !writeResult; SevMailbox = 1; LLSCLock = 0;" class StoreDoubleImm(StoreImmInst, StoreDouble): decConstBase = 'LoadStoreDImm' diff --git a/src/arch/arm/isa/insts/str64.isa b/src/arch/arm/isa/insts/str64.isa index c15dca16e..0b153c1ec 100644 --- a/src/arch/arm/isa/insts/str64.isa +++ b/src/arch/arm/isa/insts/str64.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2011-2013 ARM Limited +// Copyright (c) 2011-2013,2017 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -277,7 +277,8 @@ let {{ execBase = 'StoreEx64' def __init__(self, *args, **kargs): super(StoreEx64, self).__init__(*args, **kargs) - self.codeBlobs["postacc_code"] = "XResult = !writeResult;" + self.codeBlobs["postacc_code"] = \ + "XResult = !writeResult; SevMailbox = 1; LLSCLock = 0;" def buildStores64(mnem, NameBase, size, flavor="normal"): StoreImm64(mnem, NameBase + "_IMM", size, flavor=flavor).emit() @@ -343,7 +344,8 @@ let {{ writeback = False def __init__(self, *args, **kargs): super(StoreImmDEx64, self).__init__(*args, **kargs) - self.codeBlobs["postacc_code"] = "XResult = !writeResult;" + self.codeBlobs["postacc_code"] = \ + "XResult = !writeResult; SevMailbox = 1; LLSCLock = 0;" class StoreRegU64(StoreReg64): decConstBase = 'LoadStoreRegU64' |