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authorGiacomo Travaglini <giacomo.travaglini@arm.com>2018-10-23 13:33:12 +0100
committerGiacomo Travaglini <giacomo.travaglini@arm.com>2018-10-26 09:45:47 +0000
commit438ecf9cb08f8e5681ef39df7f6709b8fdec2d50 (patch)
tree310f6026b2534bdfa0fb55e545a87ed3c2b4dd39 /src/arch/arm/isa/insts
parent47a8c479d9b12625d4d56a0c18ba72a0b640579e (diff)
downloadgem5-438ecf9cb08f8e5681ef39df7f6709b8fdec2d50.tar.xz
arch-arm: Fix HVC trapping beahviour
This patch is fixing HVC trapping behaviour, reusing the pseudocode implementation provided in the arm arm. Change-Id: I0bc81478400b99d84534c1c8871f894722f547c5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13776 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/insts')
-rw-r--r--src/arch/arm/isa/insts/misc64.isa16
1 files changed, 13 insertions, 3 deletions
diff --git a/src/arch/arm/isa/insts/misc64.isa b/src/arch/arm/isa/insts/misc64.isa
index 2621905c7..6d40dd913 100644
--- a/src/arch/arm/isa/insts/misc64.isa
+++ b/src/arch/arm/isa/insts/misc64.isa
@@ -51,10 +51,20 @@ let {{
hvcCode = '''
SCR scr = Scr64;
+ HCR hcr = Hcr64;
+ CPSR cpsr = Cpsr;
- if (!ArmSystem::haveVirtualization(xc->tcBase()) ||
- (ArmSystem::haveSecurity(xc->tcBase()) && (!scr.ns || !scr.hce))) {
- fault = disabledFault();
+ auto tc = xc->tcBase();
+ ExceptionLevel pstate_EL = (ExceptionLevel)(uint8_t)(cpsr.el);
+
+ bool unalloc_encod = !ArmSystem::haveEL(tc, EL2) || pstate_EL == EL0 ||
+ (pstate_EL == EL1 && inSecureState(tc));
+
+ bool hvc_enable = ArmSystem::haveEL(tc, EL3) ?
+ scr.hce : !hcr.hcd;
+
+ if (unalloc_encod || !hvc_enable) {
+ fault = undefinedFault64(tc, pstate_EL);
} else {
fault = std::make_shared<HypervisorCall>(machInst, bits(machInst, 20, 5));
}