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authorGabe Black <gblack@eecs.umich.edu>2011-11-02 01:25:15 -0700
committerGabe Black <gblack@eecs.umich.edu>2011-11-02 01:25:15 -0700
commit239b33e016b19aa18e70f3bc64c4e11de3f92c7d (patch)
tree87008a6ac9437f57bb9a33b240603fe090b4b0ab /src/arch/arm/isa/insts
parent7b417d4188c4978ecdeddd04a0b53f60b96d22e1 (diff)
downloadgem5-239b33e016b19aa18e70f3bc64c4e11de3f92c7d.tar.xz
SE/FS: Get rid of FULL_SYSTEM in the ARM ISA.
Diffstat (limited to 'src/arch/arm/isa/insts')
-rw-r--r--src/arch/arm/isa/insts/div.isa18
-rw-r--r--src/arch/arm/isa/insts/m5ops.isa18
-rw-r--r--src/arch/arm/isa/insts/misc.isa51
-rw-r--r--src/arch/arm/isa/insts/neon.isa41
-rw-r--r--src/arch/arm/isa/insts/swap.isa9
5 files changed, 52 insertions, 85 deletions
diff --git a/src/arch/arm/isa/insts/div.isa b/src/arch/arm/isa/insts/div.isa
index 8a94d1ebd..1ff6ef9e4 100644
--- a/src/arch/arm/isa/insts/div.isa
+++ b/src/arch/arm/isa/insts/div.isa
@@ -41,11 +41,10 @@ let {{
sdivCode = '''
if (Op2_sw == 0) {
if (((SCTLR)Sctlr).dz) {
-#if FULL_SYSTEM
- return new UndefinedInstruction;
-#else
- return new UndefinedInstruction(false, mnemonic);
-#endif
+ if (FullSystem)
+ return new UndefinedInstruction;
+ else
+ return new UndefinedInstruction(false, mnemonic);
}
Dest_sw = 0;
} else if (Op1_sw == INT_MIN && Op2_sw == -1) {
@@ -65,11 +64,10 @@ let {{
udivCode = '''
if (Op2_uw == 0) {
if (((SCTLR)Sctlr).dz) {
-#if FULL_SYSTEM
- return new UndefinedInstruction;
-#else
- return new UndefinedInstruction(false, mnemonic);
-#endif
+ if (FullSystem)
+ return new UndefinedInstruction;
+ else
+ return new UndefinedInstruction(false, mnemonic);
}
Dest_uw = 0;
} else {
diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa
index e891a0a91..a157b414c 100644
--- a/src/arch/arm/isa/insts/m5ops.isa
+++ b/src/arch/arm/isa/insts/m5ops.isa
@@ -54,9 +54,7 @@ let {{
armCode = '''
-#if FULL_SYSTEM
PseudoInst::arm(xc->tcBase());
-#endif
'''
armIop = InstObjParams("arm", "Arm", "PredOp",
{ "code": armCode,
@@ -67,9 +65,7 @@ let {{
exec_output += PredOpExecute.subst(armIop)
quiesceCode = '''
-#if FULL_SYSTEM
PseudoInst::quiesce(xc->tcBase());
-#endif
'''
quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp",
{ "code": quiesceCode,
@@ -80,9 +76,7 @@ let {{
exec_output += QuiescePredOpExecute.subst(quiesceIop)
quiesceNsCode = '''
-#if FULL_SYSTEM
PseudoInst::quiesceNs(xc->tcBase(), join32to64(R1, R0));
-#endif
'''
quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs", "PredOp",
@@ -94,9 +88,7 @@ let {{
exec_output += QuiescePredOpExecute.subst(quiesceNsIop)
quiesceCyclesCode = '''
-#if FULL_SYSTEM
PseudoInst::quiesceCycles(xc->tcBase(), join32to64(R1, R0));
-#endif
'''
quiesceCyclesIop = InstObjParams("quiesceCycles", "QuiesceCycles", "PredOp",
@@ -108,11 +100,9 @@ let {{
exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop)
quiesceTimeCode = '''
-#if FULL_SYSTEM
uint64_t qt_val = PseudoInst::quiesceTime(xc->tcBase());
R0 = bits(qt_val, 31, 0);
R1 = bits(qt_val, 63, 32);
-#endif
'''
quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime", "PredOp",
@@ -188,9 +178,7 @@ let {{
exec_output += PredOpExecute.subst(m5exitIop)
loadsymbolCode = '''
-#if FULL_SYSTEM
PseudoInst::loadsymbol(xc->tcBase());
-#endif
'''
loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", "PredOp",
@@ -202,9 +190,7 @@ let {{
exec_output += PredOpExecute.subst(loadsymbolIop)
initparamCode = '''
-#if FULL_SYSTEM
Rt = PseudoInst::initParam(xc->tcBase());
-#endif
'''
initparamIop = InstObjParams("initparam", "Initparam", "PredOp",
@@ -260,11 +246,9 @@ let {{
exec_output += PredOpExecute.subst(m5checkpointIop)
m5readfileCode = '''
-#if FULL_SYSTEM
int n = 4;
uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false);
R0 = PseudoInst::readfile(xc->tcBase(), R0, join32to64(R3,R2), offset);
-#endif
'''
m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp",
{ "code": m5readfileCode,
@@ -291,9 +275,7 @@ let {{
exec_output += PredOpExecute.subst(m5switchcpuIop)
m5addsymbolCode = '''
-#if FULL_SYSTEM
PseudoInst::addsymbol(xc->tcBase(), join32to64(R1, R0), R2);
-#endif
'''
m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", "PredOp",
{ "code": m5addsymbolCode,
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 2cf54fcdb..495cb722c 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -40,11 +40,11 @@
let {{
svcCode = '''
-#if FULL_SYSTEM
- fault = new SupervisorCall;
-#else
- fault = new SupervisorCall(machInst);
-#endif
+ if (FullSystem) {
+ fault = new SupervisorCall;
+ } else {
+ fault = new SupervisorCall(machInst);
+ }
'''
svcIop = InstObjParams("svc", "Svc", "PredOp",
@@ -501,7 +501,6 @@ let {{
exec_output += PredOpExecute.subst(yieldIop)
wfeCode = '''
-#if FULL_SYSTEM
// WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending
if (SevMailbox == 1) {
SevMailbox = 0;
@@ -511,14 +510,11 @@ let {{
} else {
PseudoInst::quiesce(xc->tcBase());
}
-#endif
'''
wfePredFixUpCode = '''
-#if FULL_SYSTEM
// WFE is predicated false, reset SevMailbox to reduce spurious sleeps
// and SEV interrupts
SevMailbox = 1;
-#endif
'''
wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
{ "code" : wfeCode,
@@ -530,14 +526,12 @@ let {{
exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
wfiCode = '''
-#if FULL_SYSTEM
// WFI doesn't sleep if interrupts are pending (masked or not)
if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkRaw()) {
PseudoInst::quiesceSkip(xc->tcBase());
} else {
PseudoInst::quiesce(xc->tcBase());
}
-#endif
'''
wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
{ "code" : wfiCode, "predicate_test" : predicateTest },
@@ -547,7 +541,6 @@ let {{
exec_output += QuiescePredOpExecute.subst(wfiIop)
sevCode = '''
-#if FULL_SYSTEM
SevMailbox = 1;
System *sys = xc->tcBase()->getSystemPtr();
for (int x = 0; x < sys->numContexts(); x++) {
@@ -560,7 +553,6 @@ let {{
oc->getCpuPtr()->postInterrupt(INT_SEV, 0);
}
}
-#endif
'''
sevIop = InstObjParams("sev", "SevInst", "PredOp", \
{ "code" : sevCode, "predicate_test" : predicateTest },
@@ -577,11 +569,10 @@ let {{
decoder_output += BasicConstructor.subst(itIop)
exec_output += PredOpExecute.subst(itIop)
unknownCode = '''
-#if FULL_SYSTEM
- return new UndefinedInstruction;
-#else
- return new UndefinedInstruction(machInst, true);
-#endif
+ if (FullSystem)
+ return new UndefinedInstruction;
+ else
+ return new UndefinedInstruction(machInst, true);
'''
unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
{ "code": unknownCode,
@@ -634,12 +625,12 @@ let {{
mrc15code = '''
CPSR cpsr = Cpsr;
- if (cpsr.mode == MODE_USER)
-#if FULL_SYSTEM
- return new UndefinedInstruction;
-#else
- return new UndefinedInstruction(false, mnemonic);
-#endif
+ if (cpsr.mode == MODE_USER) {
+ if (FullSystem)
+ return new UndefinedInstruction;
+ else
+ return new UndefinedInstruction(false, mnemonic);
+ }
Dest = MiscOp1;
'''
@@ -653,12 +644,12 @@ let {{
mcr15code = '''
CPSR cpsr = Cpsr;
- if (cpsr.mode == MODE_USER)
-#if FULL_SYSTEM
- return new UndefinedInstruction;
-#else
- return new UndefinedInstruction(false, mnemonic);
-#endif
+ if (cpsr.mode == MODE_USER) {
+ if (FullSystem)
+ return new UndefinedInstruction;
+ else
+ return new UndefinedInstruction(false, mnemonic);
+ }
MiscDest = Op1;
'''
mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa
index fdb6237c0..9565ee14a 100644
--- a/src/arch/arm/isa/insts/neon.isa
+++ b/src/arch/arm/isa/insts/neon.isa
@@ -872,11 +872,10 @@ let {{
readDestCode = 'destElem = gtoh(destReg.elements[i]);'
eWalkCode += '''
if (imm < 0 && imm >= eCount) {
-#if FULL_SYSTEM
- fault = new UndefinedInstruction;
-#else
- fault = new UndefinedInstruction(false, mnemonic);
-#endif
+ if (FullSystem)
+ fault = new UndefinedInstruction;
+ else
+ fault = new UndefinedInstruction(false, mnemonic);
} else {
for (unsigned i = 0; i < eCount; i++) {
Element srcElem1 = gtoh(srcReg1.elements[i]);
@@ -927,11 +926,10 @@ let {{
readDestCode = 'destElem = gtoh(destReg.elements[i]);'
eWalkCode += '''
if (imm < 0 && imm >= eCount) {
-#if FULL_SYSTEM
- fault = new UndefinedInstruction;
-#else
- fault = new UndefinedInstruction(false, mnemonic);
-#endif
+ if (FullSystem)
+ fault = new UndefinedInstruction;
+ else
+ fault = new UndefinedInstruction(false, mnemonic);
} else {
for (unsigned i = 0; i < eCount; i++) {
Element srcElem1 = gtoh(srcReg1.elements[i]);
@@ -980,11 +978,10 @@ let {{
readDestCode = 'destReg = destRegs[i];'
eWalkCode += '''
if (imm < 0 && imm >= eCount) {
-#if FULL_SYSTEM
- fault = new UndefinedInstruction;
-#else
- fault = new UndefinedInstruction(false, mnemonic);
-#endif
+ if (FullSystem)
+ fault = new UndefinedInstruction;
+ else
+ fault = new UndefinedInstruction(false, mnemonic);
} else {
for (unsigned i = 0; i < rCount; i++) {
FloatReg srcReg1 = srcRegs1[i];
@@ -3298,14 +3295,14 @@ let {{
destReg.elements[i] = srcReg1.elements[index];
} else {
index -= eCount;
- if (index >= eCount)
-#if FULL_SYSTEM
- fault = new UndefinedInstruction;
-#else
- fault = new UndefinedInstruction(false, mnemonic);
-#endif
- else
+ if (index >= eCount) {
+ if (FullSystem)
+ fault = new UndefinedInstruction;
+ else
+ fault = new UndefinedInstruction(false, mnemonic);
+ } else {
destReg.elements[i] = srcReg2.elements[index];
+ }
}
}
'''
diff --git a/src/arch/arm/isa/insts/swap.isa b/src/arch/arm/isa/insts/swap.isa
index f319e75aa..b42a1c4b2 100644
--- a/src/arch/arm/isa/insts/swap.isa
+++ b/src/arch/arm/isa/insts/swap.isa
@@ -73,11 +73,10 @@ let {{
swpPreAccCode = '''
if (!((SCTLR)Sctlr).sw) {
-#if FULL_SYSTEM
- return new UndefinedInstruction;
-#else
- return new UndefinedInstruction(false, mnemonic);
-#endif
+ if (FullSystem)
+ return new UndefinedInstruction;
+ else
+ return new UndefinedInstruction(false, mnemonic);
}
'''