summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa/insts
diff options
context:
space:
mode:
authorGiacomo Travaglini <giacomo.travaglini@arm.com>2017-11-10 15:35:26 +0000
committerGiacomo Travaglini <giacomo.travaglini@arm.com>2017-11-21 14:25:56 +0000
commit2a2c66c16c659af4c3588b6c1646d55c66ad53fe (patch)
tree633dd84e28b040febbe2fd2efc7cd0a62dc7f60d /src/arch/arm/isa/insts
parentd3ec34201c14d551e864372a89ccddb1c255e77a (diff)
downloadgem5-2a2c66c16c659af4c3588b6c1646d55c66ad53fe.tar.xz
arch-arm: Fix MSR/MRS disassemble
This patch is fixing the Aarch64 MSR/MRS disassemble, which was previously printing unexisting integer registers as source/destination operands rather than the system register name Change-Id: Iac9d5f2f2fea85abd9a398320ef7aa4844d43c0e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5861 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/insts')
-rw-r--r--src/arch/arm/isa/insts/data64.isa25
1 files changed, 19 insertions, 6 deletions
diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa
index d0ee439cb..887130f77 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -351,15 +351,21 @@ let {{
}
'''
- buildDataXImmInst("mrs", '''
+ mrsCode = '''
MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
flattenRegId(RegId(MiscRegClass, op1)).index();
CPSR cpsr = Cpsr;
ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
%s
XDest = MiscOp1_ud;
- ''' % (msrMrs64EnabledCheckCode % ('Read', 'true'),),
- ["IsSerializeBefore"])
+ ''' % (msrMrs64EnabledCheckCode % ('Read', 'true'),)
+
+ mrsIop = InstObjParams("mrs", "Mrs64", "RegMiscRegImmOp64",
+ mrsCode,
+ ["IsSerializeBefore"])
+ header_output += RegMiscRegOp64Declare.subst(mrsIop)
+ decoder_output += RegMiscRegOp64Constructor.subst(mrsIop)
+ exec_output += BasicExecute.subst(mrsIop)
buildDataXRegInst("mrsNZCV", 1, '''
CPSR cpsr = 0;
@@ -369,15 +375,22 @@ let {{
XDest = cpsr;
''')
- buildDataXImmInst("msr", '''
+ msrCode = '''
MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
flattenRegId(RegId(MiscRegClass, dest)).index();
CPSR cpsr = Cpsr;
ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
%s
MiscDest_ud = XOp1;
- ''' % (msrMrs64EnabledCheckCode % ('Write', 'false'),),
- ["IsSerializeAfter", "IsNonSpeculative"])
+ ''' % (msrMrs64EnabledCheckCode % ('Write', 'false'),)
+
+ msrIop = InstObjParams("msr", "Msr64", "MiscRegRegImmOp64",
+ msrCode,
+ ["IsSerializeAfter", "IsNonSpeculative"])
+ header_output += MiscRegRegOp64Declare.subst(msrIop)
+ decoder_output += MiscRegRegOp64Constructor.subst(msrIop)
+ exec_output += BasicExecute.subst(msrIop)
+
buildDataXRegInst("msrNZCV", 1, '''
CPSR cpsr = XOp1;