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authorGabe Black <gabeblack@google.com>2017-11-04 03:45:23 -0700
committerGabe Black <gabeblack@google.com>2017-11-07 01:31:24 +0000
commit344911b885114b8401482679202aaee89fa8b29b (patch)
tree395424b6f248c24977462489c8c1e3c1e97e7c34 /src/arch/arm/isa/insts
parent7e02ab1dc622081a30e5b8bec3a944bd1fc7fca6 (diff)
downloadgem5-344911b885114b8401482679202aaee89fa8b29b.tar.xz
alpha,arm,mips,power,riscv,sparc,x86: Merge exec decl templates.
In the ISA instruction definitions, some classes were declared with execute, etc., functions outside of the main template because they had CPU specific signatures and would need to be duplicated with each CPU plugged into them. Now that the instructions always just use an ExecContext, there's no reason for those templates to be separate. This change folds those templates together. Change-Id: I13bda247d3d1cc07c0ea06968e48aa5b4aace7fa Reviewed-on: https://gem5-review.googlesource.com/5401 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/insts')
-rw-r--r--src/arch/arm/isa/insts/fp.isa8
1 files changed, 0 insertions, 8 deletions
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index dff906755..dcf5889fb 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -60,8 +60,6 @@ class VfpMacroRegRegOp : public VfpMacroOp
nextIdxs(_dest, _op1);
}
}
-
- %(BasicExecPanic)s
};
template <class VfpOp>
@@ -96,8 +94,6 @@ class VfpMacroRegImmOp : public VfpMacroOp
nextIdxs(_dest);
}
}
-
- %(BasicExecPanic)s
};
template <class VfpOp>
@@ -132,8 +128,6 @@ class VfpMacroRegRegImmOp : public VfpMacroOp
nextIdxs(_dest, _op1);
}
}
-
- %(BasicExecPanic)s
};
template <class VfpOp>
@@ -168,8 +162,6 @@ class VfpMacroRegRegRegOp : public VfpMacroOp
nextIdxs(_dest, _op1, _op2);
}
}
-
- %(BasicExecPanic)s
};
template <class VfpOp>