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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-01-09 10:10:04 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-02-07 15:13:49 +0000 |
| commit | 7798ffb6948d12c7f2bc63dc9a3263bb19aa3297 (patch) | |
| tree | 24e2a42dc06b980a86e7763b6b01d9fd7aa372e0 /src/arch/arm/isa/insts | |
| parent | 633fdd5841d8e7798e1b1158261612a6ad84c812 (diff) | |
| download | gem5-7798ffb6948d12c7f2bc63dc9a3263bb19aa3297.tar.xz | |
arch-arm: Change function name for banked miscregs
This commit changes the function's name used for retrieving the index of a
security banked register given the flatten index. This will avoid confusion
with flattenRegId, which has a different purpose.
Change-Id: I470ffb55916cb7fc9f78e071a7f2e609c1829f1a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7982
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/insts')
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 23962b02d..8745e86bc 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -872,7 +872,7 @@ let {{ exec_output += PredOpExecute.subst(mcr14Iop) mrc15code = ''' - int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase()); + int preFlatOp1 = snsBankedIndex(op1, xc->tcBase()); MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(RegId(MiscRegClass, preFlatOp1)).index(); @@ -904,7 +904,7 @@ let {{ mcr15code = ''' - int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase()); + int preFlatDest = snsBankedIndex(dest, xc->tcBase()); MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(RegId(MiscRegClass, preFlatDest)).index(); @@ -937,7 +937,7 @@ let {{ mrrc15code = ''' - int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase()); + int preFlatOp1 = snsBankedIndex(op1, xc->tcBase()); MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(RegId(MiscRegClass, preFlatOp1)).index(); @@ -968,7 +968,7 @@ let {{ mcrr15code = ''' - int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase()); + int preFlatDest = snsBankedIndex(dest, xc->tcBase()); MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(RegId(MiscRegClass, preFlatDest)).index(); @@ -1045,7 +1045,7 @@ let {{ exec_output += PredOpExecute.subst(clrexIop) McrDcCheckCode = ''' - int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase()); + int preFlatDest = snsBankedIndex(dest, xc->tcBase()); MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId( RegId(MiscRegClass, preFlatDest)).index(); bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr, |