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authorNikos Nikoleris <nikos.nikoleris@arm.com>2017-12-19 21:49:08 +0000
committerNikos Nikoleris <nikos.nikoleris@arm.com>2018-02-07 16:14:39 +0000
commitc364f58da916a6a1cb66c3e0276e898d77e1021b (patch)
treeacb02a2876489805fa17db918f20ef5693f62b0a /src/arch/arm/isa/insts
parent4d9811cc5fd36a972e340ad82b14ab0ccaeb5cfa (diff)
downloadgem5-c364f58da916a6a1cb66c3e0276e898d77e1021b.tar.xz
arch-arm: Turn dc ivac to dc civac when some conditions are met
The Arm ARM defines that at EL1 a data cache invalidate instruction performs a data cache clean and invalidate operation if all of the following apply: * EL2 is implemented, * HCR_EL2.VM is set to 1, * SCR_EL3.NS is set to 1 or EL3 is not implemented. This changeset implements this behavior. Change-Id: I6b6aef2f4b1e7eb107c069fdb0a10f4aa8e6b196 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7826 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/insts')
-rw-r--r--src/arch/arm/isa/insts/data64.isa8
1 files changed, 7 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa
index dd87bed62..af84f6566 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2011-2013, 2016-2017 ARM Limited
+// Copyright (c) 2011-2013, 2016-2018 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -524,6 +524,12 @@ let {{
Request::Flags memAccessFlags = Request::INVALIDATE |
Request::DST_POC | ArmISA::TLB::MustBeOne;
EA = XBase;
+ HCR hcr = Hcr64;
+ SCR scr = Scr64;
+ if (el == EL1 && ArmSystem::haveVirtualization(xc->tcBase()) &&
+ hcr.vm && (scr.ns || !ArmSystem::haveSecurity(xc->tcBase()))) {
+ memAccessFlags = memAccessFlags | Request::CLEAN;
+ }
System *sys = xc->tcBase()->getSystemPtr();
Addr op_size = sys->cacheLineSize();
EA &= ~(op_size - 1);