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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:04 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:04 -0500
commitd63f748b5361df3fb84ba5274ab89a642cec2dfb (patch)
tree27e5e96a9223b581bc419115e9331ab818f85982 /src/arch/arm/isa/insts
parente92dc21fde1b9561019236699106d719866665b8 (diff)
downloadgem5-d63f748b5361df3fb84ba5274ab89a642cec2dfb.tar.xz
ARM: Implement ADR as separate from ADD.
Diffstat (limited to 'src/arch/arm/isa/insts')
-rw-r--r--src/arch/arm/isa/insts/data.isa4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa
index a3418edf0..02ecd6b4c 100644
--- a/src/arch/arm/isa/insts/data.isa
+++ b/src/arch/arm/isa/insts/data.isa
@@ -200,6 +200,10 @@ let {{
buildDataInst("sub", "AIWDest = resTemp = Op1 - secondOp;", "sub")
buildDataInst("rsb", "AIWDest = resTemp = secondOp - Op1;", "rsb")
buildDataInst("add", "AIWDest = resTemp = Op1 + secondOp;", "add")
+ buildImmDataInst("adr", '''
+ AIWDest = resTemp = (readPC(xc) & ~0x3) +
+ (op1 ? secondOp : -secondOp);
+ ''')
buildDataInst("adc", "AIWDest = resTemp = Op1 + secondOp + %s;" % oldC,
"add")
buildDataInst("sbc", "AIWDest = resTemp = Op1 - secondOp - !%s;" % oldC,