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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-05-09 11:52:05 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-09 09:12:28 +0000 |
| commit | dd63d6d932894047f3f9f8534fe16619ceed8ff4 (patch) | |
| tree | eac2e89a30225369d66a79658c0a00c2f7a6b810 /src/arch/arm/isa/insts | |
| parent | 52bab3f6eb87bca3b3b79e28f516da9e79445d07 (diff) | |
| download | gem5-dd63d6d932894047f3f9f8534fe16619ceed8ff4.tar.xz | |
arch-arm: AArch64 Crypto AES
This patch implements the AArch64 AES instructions
from the Crypto extension.
Change-Id: I9143041ec7e1c6a50dcad3f72d7d1b55d6f2d402
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13250
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/insts')
| -rw-r--r-- | src/arch/arm/isa/insts/crypto64.isa | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/crypto64.isa b/src/arch/arm/isa/insts/crypto64.isa index 1af9263fd..64beaf33d 100644 --- a/src/arch/arm/isa/insts/crypto64.isa +++ b/src/arch/arm/isa/insts/crypto64.isa @@ -120,6 +120,11 @@ let {{ decoder_output += RegRegOpConstructor.subst(cryptoiop) exec_output += CryptoPredOpExecute.subst(cryptoiop) + aeseCode = "crypto.aesEncrypt(output, input, input2);" + aesdCode = "crypto.aesDecrypt(output, input, input2);" + aesmcCode = "crypto.aesMixColumns(output, input);" + aesimcCode = "crypto.aesInvMixColumns(output, input);" + sha1_cCode = "crypto.sha1C(output, input, input2);" sha1_pCode = "crypto.sha1P(output, input, input2);" sha1_mCode = "crypto.sha1M(output, input, input2);" @@ -132,6 +137,16 @@ let {{ sha256_su0Code = "crypto.sha256Su0(output, input);" sha256_su1Code = "crypto.sha256Su1(output, input, input2);" + aes_enabled = cryptoEnabledCheckCode % { "mask" : 0xF0 } + cryptoRegRegRegInst("aese", "AESE64", "SimdAesOp", + aes_enabled, aeseCode) + cryptoRegRegRegInst("aesd", "AESD64", "SimdAesOp", + aes_enabled, aesdCode) + cryptoRegRegInst("aesmc", "AESMC64", "SimdAesMixOp", + aes_enabled, aesmcCode) + cryptoRegRegInst("aesimc", "AESIMC64", "SimdAesMixOp", + aes_enabled, aesimcCode) + sha1_enabled = cryptoEnabledCheckCode % { "mask" : 0xF00 } cryptoRegRegRegInst("sha1c", "SHA1C64", "SimdSha1HashOp", sha1_enabled, sha1_cCode) |