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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:10 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:10 -0500 |
| commit | 3caa75d53aa9c04b238aeae281983d8b73754e98 (patch) | |
| tree | 6b1b240a3127872b86262db4342d32d4be0dfc85 /src/arch/arm/isa/operands.isa | |
| parent | 36eeee013339141994ef3091c4b3726d08395f04 (diff) | |
| download | gem5-3caa75d53aa9c04b238aeae281983d8b73754e98.tar.xz | |
ARM: Squash the low order bits of the PC when performing a regular branch.
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 1a98a9087..a8b0b197a 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -70,10 +70,11 @@ let {{ ''' maybeAIWPCWrite = ''' if (%(reg_idx)s == PCReg) { - if (xc->readPC() & (ULL(1) << PcTBitShift)) { - setIWNextPC(xc, %(final_val)s); - } else { + bool thumb = THUMB; + if (thumb) { setNextPC(xc, %(final_val)s); + } else { + setIWNextPC(xc, %(final_val)s); } } else { xc->%(func)s(this, %(op_idx)s, %(final_val)s); |