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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:19 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:19 -0700 |
| commit | 70a75ceb84c3c1964db548a254e2b6abdf8c084c (patch) | |
| tree | 42ffe6531449f4781962c1b13e9d7ab2e34ccf3f /src/arch/arm/isa/operands.isa | |
| parent | 4eb18cc07acdd3cbb64770d04c8ed7da50fae146 (diff) | |
| download | gem5-70a75ceb84c3c1964db548a254e2b6abdf8c084c.tar.xz | |
ARM: Move the integer microops out of the decoder and into the ISA desc.
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 18295cf61..c9df79e1e 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -56,6 +56,10 @@ def operands {{ 'Rlo': ('IntReg', 'uw', '19', 'IsInteger', 8), 'LR': ('IntReg', 'uw', '14', 'IsInteger', 9), + #Register fields for microops + 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11), + 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12), + #General Purpose Floating Point Reg Operands 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20), 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21), |