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author | Ali Saidi <saidi@eecs.umich.edu> | 2009-07-27 00:51:01 -0700 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2009-07-27 00:51:01 -0700 |
commit | 99831ed93821ee8efc3e7a4b6671c5b226d245e2 (patch) | |
tree | e9945e22340dc1c1c2f32d74720371dc4d078819 /src/arch/arm/isa/operands.isa | |
parent | 0a18bc0d6cdcbf68f9bf01ae98ce0f678c62f16f (diff) | |
download | gem5-99831ed93821ee8efc3e7a4b6671c5b226d245e2.tar.xz |
ARM: Handle register indexed system calls.
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
-rw-r--r-- | src/arch/arm/isa/operands.isa | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index fa41918c1..6e6eea5a8 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -57,6 +57,7 @@ def operands {{ 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite), 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite), + 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5), #Destination register for load/store double instructions 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite), |