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authorGabe Black <gblack@eecs.umich.edu>2010-08-25 19:10:42 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-08-25 19:10:42 -0500
commit63464d950ec4e8b8f3aa86802ca9fbf1e8c662b6 (patch)
tree62269c4404c83a2a371f3d73fc58ff496d472c90 /src/arch/arm/isa/operands.isa
parent93ce7238bf25b4f75f129aa822c70591a0b15a31 (diff)
downloadgem5-63464d950ec4e8b8f3aa86802ca9fbf1e8c662b6.tar.xz
ARM: Seperate out the renamable bits in the FPSCR.
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
-rw-r--r--src/arch/arm/isa/operands.isa1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 7b2b50290..4f1b7f610 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -182,6 +182,7 @@ def operands {{
'OptCondCodes': ('IntReg', 'uw',
'''(condCode == COND_AL || condCode == COND_UC) ?
INTREG_ZERO : INTREG_CONDCODES''', None, 2),
+ 'FpCondCodes': ('IntReg', 'uw', 'INTREG_FPCONDCODES', None, 2),
#Register fields for microops
'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, maybePCRead, maybePCWrite),