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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-11-08 01:59:20 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-11-08 01:59:20 -0800 |
| commit | 78bd8fe44fe3398f361335d2feb59a8221cc52e8 (patch) | |
| tree | 9c4cb010c832d9b09901e15f2129c0fca427b4a6 /src/arch/arm/isa/operands.isa | |
| parent | f63c260d89591d8d57274bb37aea51dc7c093b8f (diff) | |
| download | gem5-78bd8fe44fe3398f361335d2feb59a8221cc52e8.tar.xz | |
ARM: Add back in spots for Rhi and Rlo, and use a named constant for LR.
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index a4c404bd5..4ac6790e5 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -63,9 +63,9 @@ def operands {{ 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite), 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite), - 'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 7), - 'Rlo': ('IntReg', 'uw', '19', 'IsInteger', 8), - 'LR': ('IntReg', 'uw', '14', 'IsInteger', 9), + 'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7), + 'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8), + 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9), #Register fields for microops 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite), |