summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa/operands.isa
diff options
context:
space:
mode:
authorAli Saidi <Ali.Saidi@ARM.com>2011-05-13 17:27:01 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2011-05-13 17:27:01 -0500
commit2178859b76bb13b1d225fc4dffa04d43d2db2e14 (patch)
treec57a005891e10565c9e7552cb90037a667001807 /src/arch/arm/isa/operands.isa
parent4bf48a11efd7253bdb7a61da42d2bc754033757b (diff)
downloadgem5-2178859b76bb13b1d225fc4dffa04d43d2db2e14.tar.xz
ARM: Break up condition codes into normal flags, saturation, and simd.
This change splits out the condcodes from being one monolithic register into three blocks that are updated independently. This allows CPUs to not have to do RMW operations on the flags registers for instructions that don't write all flags.
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
-rw-r--r--src/arch/arm/isa/operands.isa8
1 files changed, 5 insertions, 3 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index b497564b7..9053f6e92 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -156,10 +156,12 @@ def operands {{
'R3': intRegNPC('3'),
#Pseudo integer condition code registers
- 'CondCodes': intRegCC('INTREG_CONDCODES'),
- 'OptCondCodes': intRegCC(
+ 'CondCodesF': intRegCC('INTREG_CONDCODES_F'),
+ 'CondCodesQ': intRegCC('INTREG_CONDCODES_Q'),
+ 'CondCodesGE': intRegCC('INTREG_CONDCODES_GE'),
+ 'OptCondCodesF': intRegCC(
'''(condCode == COND_AL || condCode == COND_UC) ?
- INTREG_ZERO : INTREG_CONDCODES'''),
+ INTREG_ZERO : INTREG_CONDCODES_F'''),
'FpCondCodes': intRegCC('INTREG_FPCONDCODES'),
#Abstracted floating point reg operands