diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2009-11-10 23:44:05 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-11-10 23:44:05 -0800 |
| commit | 5524af83efab8ee502f84987d56306ecd140ab80 (patch) | |
| tree | 7de595bd61e59122447c5ecabdaa92a52135a25e /src/arch/arm/isa/operands.isa | |
| parent | 850eb54a7c3408b887a0f6663c021fd61f227204 (diff) | |
| download | gem5-5524af83efab8ee502f84987d56306ecd140ab80.tar.xz | |
ARM: Fix some bugs in the ISA desc and fill out some instructions.
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 02acc8ed7..5ae0b8912 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -58,6 +58,7 @@ def operands {{ 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite), 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite), 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5), + 'R0': ('IntReg', 'uw', '0', 'IsInteger', 0), #Destination register for load/store double instructions 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite), |