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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
| commit | 3e2cad8370d99f45ecf4d922d3ac8213e0d72644 (patch) | |
| tree | 34a230e7364e94cb179cd07d1f8353a83dab4247 /src/arch/arm/isa/operands.isa | |
| parent | b8b7c7314ab6b7d9c7dc5315858274dc4c6b02ad (diff) | |
| download | gem5-3e2cad8370d99f45ecf4d922d3ac8213e0d72644.tar.xz | |
ARM: Use custom read/write code to alias R15 with the PC.
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 27 |
1 files changed, 19 insertions, 8 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index c9df79e1e..fa41918c1 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -40,16 +40,27 @@ def operand_types {{ 'df' : ('float', 64) }}; +let {{ + maybePCRead = ''' + ((%(reg_idx)s == PCReg) ? (xc->readPC() + 8) : + xc->%(func)s(this, %(op_idx)s)) + ''' + maybePCWrite = ''' + ((%(reg_idx)s == PCReg) ? xc->setNextPC(%(final_val)s) : + xc->%(func)s(this, %(op_idx)s, %(final_val)s)) + ''' +}}; + def operands {{ #General Purpose Integer Reg Operands - 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1), - 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2), - 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3), - 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4), + 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite), + 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), + 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite), + 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite), #Destination register for load/store double instructions - 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4), - 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5), + 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite), + 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite), 'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 6), 'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 7), @@ -57,8 +68,8 @@ def operands {{ 'LR': ('IntReg', 'uw', '14', 'IsInteger', 9), #Register fields for microops - 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11), - 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12), + 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite), + 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite), #General Purpose Floating Point Reg Operands 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20), |