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| author | Matt Horsnell <Matt.Horsnell@arm.com> | 2011-03-17 19:20:19 -0500 |
|---|---|---|
| committer | Matt Horsnell <Matt.Horsnell@arm.com> | 2011-03-17 19:20:19 -0500 |
| commit | e65f480d62e0112e89af6130e2f2024d89417df0 (patch) | |
| tree | 2697b4961dca930ebdd77fe40fdcc6a1d19db115 /src/arch/arm/isa/operands.isa | |
| parent | 799c3da8d0086bfdfbae532e05018828387e4497 (diff) | |
| download | gem5-e65f480d62e0112e89af6130e2f2024d89417df0.tar.xz | |
ARM: Rename registers used as temporary state by microops.
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index f403f9372..7b014acd0 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -228,11 +228,11 @@ def operands {{ 'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'), #Register fields for microops - 'Ra' : intReg('ura'), + 'URa' : intReg('ura'), 'IWRa' : intRegIWPC('ura'), 'Fa' : floatReg('ura'), - 'Rb' : intReg('urb'), - 'Rc' : intReg('urc'), + 'URb' : intReg('urb'), + 'URc' : intReg('urc'), #Memory Operand 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal), |