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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:03 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:03 -0500 |
| commit | 33da368e99955230a7d83c33c49c42fb59ec5015 (patch) | |
| tree | f2102c7666ce7d8af67cf4ce3b8efcb8c3fbce6a /src/arch/arm/isa/operands.isa | |
| parent | 50229be27f38eaf563cdecf99a40aac2e0af5726 (diff) | |
| download | gem5-33da368e99955230a7d83c33c49c42fb59ec5015.tar.xz | |
ARM: Implement all integer multiply instructions.
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index ab4d95d47..2621106ac 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -89,6 +89,14 @@ def operands {{ maybePCRead, maybePCWrite), 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5, maybePCRead, maybePCWrite), + 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 6, + maybePCRead, maybePCWrite), + 'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 7, + maybePCRead, maybePCWrite), + 'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 8, + maybePCRead, maybePCWrite), + 'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 9, + maybePCRead, maybePCWrite), #General Purpose Integer Reg Operands 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite), 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), |