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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:04 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:04 -0500 |
| commit | 3a11412c995f462b9fc7eb7b688cb7d7e0011680 (patch) | |
| tree | ded66c89f8515b41b7d83ec6de469b0a3e722d83 /src/arch/arm/isa/operands.isa | |
| parent | d5aee75efe68c37224eebb0c2f8e1c5fa3ba0d1e (diff) | |
| download | gem5-3a11412c995f462b9fc7eb7b688cb7d7e0011680.tar.xz | |
ARM: Add an fp version of one of the microop indexed registers.
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index d80c0c712..84bd81ca0 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -114,6 +114,7 @@ def operands {{ #Register fields for microops 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite), + 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 11), 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite), #General Purpose Floating Point Reg Operands |