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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
| commit | 401165c778108ab22aeeee55c4f4451ca93bcffb (patch) | |
| tree | f525ba64108f6ebe208a04d2dee7b77621cafd96 /src/arch/arm/isa/operands.isa | |
| parent | e097c4fb188fafc9cd2253500ab2d056da886c9c (diff) | |
| download | gem5-401165c778108ab22aeeee55c4f4451ca93bcffb.tar.xz | |
ARM: Further break up condition code into NZ, C, V bits.
Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 21 |
1 files changed, 17 insertions, 4 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index ead058b4c..058cc94f3 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -156,11 +156,24 @@ def operands {{ 'R3': intRegNPC('3'), #Pseudo integer condition code registers - 'CondCodesF': intRegCC('INTREG_CONDCODES_F'), + 'CondCodesNZ': intRegCC('INTREG_CONDCODES_NZ'), + 'CondCodesC': intRegCC('INTREG_CONDCODES_C'), + 'CondCodesV': intRegCC('INTREG_CONDCODES_V'), 'CondCodesGE': intRegCC('INTREG_CONDCODES_GE'), - 'OptCondCodesF': intRegCC( - '''(condCode == COND_AL || condCode == COND_UC) ? - INTREG_ZERO : INTREG_CONDCODES_F'''), + 'OptCondCodesNZ': intRegCC( + '''(condCode == COND_AL || condCode == COND_UC || + condCode == COND_CC || condCode == COND_CS || + condCode == COND_VS || condCode == COND_VC) ? + INTREG_ZERO : INTREG_CONDCODES_NZ'''), + 'OptCondCodesC': intRegCC( + '''(condCode == COND_HI || condCode == COND_LS || + condCode == COND_CS || condCode == COND_CC) ? + INTREG_CONDCODES_C : INTREG_ZERO'''), + 'OptCondCodesV': intRegCC( + '''(condCode == COND_VS || condCode == COND_VC || + condCode == COND_GE || condCode == COND_LT || + condCode == COND_GT || condCode == COND_LE) ? + INTREG_CONDCODES_V : INTREG_ZERO'''), 'FpCondCodes': intRegCC('INTREG_FPCONDCODES'), #Abstracted floating point reg operands |