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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:10 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:10 -0500 |
| commit | 54ab07e636a0e83527a87c5d88406e3b443b2e99 (patch) | |
| tree | 328ec84643a3a0149b39c49b893a9ccc4f8d9729 /src/arch/arm/isa/operands.isa | |
| parent | 524a8195e18f17ee6e57bfbcb2752ac6bfa2d8ee (diff) | |
| download | gem5-54ab07e636a0e83527a87c5d88406e3b443b2e99.tar.xz | |
ARM: Implement the strex instructions.
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index a8b0b197a..3fda93668 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -91,6 +91,8 @@ def operands {{ #Abstracted integer reg operands 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 2, maybePCRead, maybePCWrite), + 'Result': ('IntReg', 'uw', 'result', 'IsInteger', 2, + maybePCRead, maybePCWrite), 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 2, maybePCRead, maybePCWrite), 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2, |