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| author | Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> | 2010-12-07 16:19:57 -0800 |
|---|---|---|
| committer | Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> | 2010-12-07 16:19:57 -0800 |
| commit | 719f9a6d4fba16af38dcfd62b25a4d708156699f (patch) | |
| tree | 1a380efa6ed27b505fdf402e2a069d217c9a4eac /src/arch/arm/isa/operands.isa | |
| parent | 4bbdd6ceb2639fe21408ab211b7c4c7e53adb249 (diff) | |
| download | gem5-719f9a6d4fba16af38dcfd62b25a4d708156699f.tar.xz | |
O3: Make all instructions that write a misc. register not perform the write until commit.
ARM instructions updating cumulative flags (ARM FP exceptions and saturation
flags) are not serialized.
Added aliases for ARM FP exceptions and saturation flags in FPSCR. Removed
write accesses to the FP condition codes for most ARM VFP instructions: only
VCMP and VCMPE instructions update the FP condition codes. Removed a potential
cause of seg. faults in the O3 model for NEON memory macro-ops (ARM).
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 3c32d98d1..dfbf173b8 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -203,6 +203,8 @@ def operands {{ 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 3), 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 3), 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 3), + 'FpscrQc': ('ControlReg', 'uw', 'MISCREG_FPSCR_QC', None, 3), + 'FpscrExc': ('ControlReg', 'uw', 'MISCREG_FPSCR_EXC', None, 3), 'Cpacr': ('ControlReg', 'uw', 'MISCREG_CPACR', (None, None, 'IsControl'), 3), 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 3), 'Sctlr': ('ControlReg', 'uw', 'MISCREG_SCTLR', None, 3), |