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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-06-21 09:21:07 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-06-21 09:21:07 -0700 |
| commit | 71e0d1ded278a85e33a628ddc842c975a216854f (patch) | |
| tree | 38b6d745885794a55021ab2f80f565dd4ed89fa8 /src/arch/arm/isa/operands.isa | |
| parent | 19a1966079442ccbcda70c33bbcead7abb609985 (diff) | |
| download | gem5-71e0d1ded278a85e33a628ddc842c975a216854f.tar.xz | |
ARM: Pull some static code out of the isa desc and create miscregs.hh.
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index b2c4f8420..f82e49109 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -64,8 +64,8 @@ def operands {{ #Memory Operand 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8), - 'Cpsr': ('ControlReg', 'uw', 'CPSR', 'IsInteger', 7), - 'Fpsr': ('ControlReg', 'uw', 'FPSR', 'IsInteger', 7), + 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 7), + 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 7), 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 9), 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 9), |