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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:07 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:07 -0500 |
| commit | c643b1c2749703b7823d665a7d89d0333f5c6e95 (patch) | |
| tree | cb9f0c6bbe54fae00f0803830bc9b2a04eea2bf3 /src/arch/arm/isa/operands.isa | |
| parent | 64ade8316ee563448d8c8f98a70cc4d9d0c66707 (diff) | |
| download | gem5-c643b1c2749703b7823d665a7d89d0333f5c6e95.tar.xz | |
ARM: Add a base class to support usada8.
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index c845acc94..e2b73e2e2 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -102,6 +102,8 @@ def operands {{ maybePCRead, maybePCWrite), 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4, maybePCRead, maybePCWrite), + 'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 4, + maybePCRead, maybePCWrite), 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5, maybePCRead, maybePCWrite), 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 6, |