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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:04 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:04 -0500 |
| commit | e92dc21fde1b9561019236699106d719866665b8 (patch) | |
| tree | f217fe849a9d022e15b9d6620c16457ef2bf0844 /src/arch/arm/isa/operands.isa | |
| parent | 11c3361be431b3f7a8aa5a628d04cb5639d4c571 (diff) | |
| download | gem5-e92dc21fde1b9561019236699106d719866665b8.tar.xz | |
ARM: Add support for interworking branch ALU instructions.
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 84bd81ca0..6e792f725 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -64,6 +64,17 @@ let {{ ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) : xc->%(func)s(this, %(op_idx)s, %(final_val)s)) ''' + maybeAIWPCWrite = ''' + if (%(reg_idx)s == PCReg) { + if (xc->readPC() & (ULL(1) << PcTBitShift)) { + setIWNextPC(xc, %(final_val)s); + } else { + setNextPC(xc, %(final_val)s); + } + } else { + xc->%(func)s(this, %(op_idx)s, %(final_val)s); + } + ''' readNPC = 'xc->readNextPC() & ~PcModeMask' writeNPC = 'setNextPC(xc, %(final_val)s)' @@ -78,7 +89,7 @@ def operands {{ 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, maybePCRead, maybeIWPCWrite), 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, - maybePCRead, maybeIWPCWrite), + maybePCRead, maybeAIWPCWrite), 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1, maybePCRead, maybePCWrite), 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2, |