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authorGabe Black <gabeblack@google.com>2017-12-13 00:53:34 -0800
committerGabe Black <gabeblack@google.com>2017-12-13 23:51:59 +0000
commitf6486a1bbe7714850980b9669d44ef8dec343a2a (patch)
tree8b782bd047fb997f1bd6c3dd8cdc8e39de288c92 /src/arch/arm/isa/operands.isa
parent93a168c25e5bb396ee749d25a2ab80ce7bec1764 (diff)
downloadgem5-f6486a1bbe7714850980b9669d44ef8dec343a2a.tar.xz
arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.
Replace them with std::array<>s. Change-Id: I76624c87a1cd9b21c386a96147a18de92b8a8a34 Reviewed-on: https://gem5-review.googlesource.com/6602 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
-rw-r--r--src/arch/arm/isa/operands.isa2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 2e2955a80..babf0accf 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -47,7 +47,7 @@ def operand_types {{
'sw' : 'int32_t',
'uw' : 'uint32_t',
'ud' : 'uint64_t',
- 'tud' : 'Twin64_t',
+ 'tud' : 'std::array<uint64_t, 2>',
'sf' : 'float',
'df' : 'double',
'vc' : 'TheISA::VecRegContainer',