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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-01-18 16:30:02 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-01-18 16:30:02 -0600 |
| commit | 0f9a3671b6d12f887501bc80ca50bb23c383686d (patch) | |
| tree | 5406b672b12e85c0654362272350cb50057be595 /src/arch/arm/isa/templates/basic.isa | |
| parent | 96375409ea7a5593ddd7f4f723db349921f35142 (diff) | |
| download | gem5-0f9a3671b6d12f887501bc80ca50bb23c383686d.tar.xz | |
ARM: Add support for moving predicated false dest operands from sources.
Diffstat (limited to 'src/arch/arm/isa/templates/basic.isa')
| -rw-r--r-- | src/arch/arm/isa/templates/basic.isa | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/arch/arm/isa/templates/basic.isa b/src/arch/arm/isa/templates/basic.isa index 843f90840..0728b66e3 100644 --- a/src/arch/arm/isa/templates/basic.isa +++ b/src/arch/arm/isa/templates/basic.isa @@ -52,6 +52,11 @@ def template BasicConstructor {{ inline %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) { %(constructor)s; + if (!(condCode == COND_AL || condCode == COND_UC)) { + for (int x = 0; x < _numDestRegs; x++) { + _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; + } + } } }}; |