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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:03 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:03 -0500
commitb02c7f1bcd4fab4097b9b4b99d08a8287ae25ca8 (patch)
tree9bbeb7c44dc6e59a030cea4d5c7e5c3c30a5e289 /src/arch/arm/isa/templates/macromem.isa
parent7b62e9ad7180bd6365c096040114a2f1dfc19fa8 (diff)
downloadgem5-b02c7f1bcd4fab4097b9b4b99d08a8287ae25ca8.tar.xz
ARM: Move the macro mem constructor out of the isa desc.
This code doesn't use the parser at all, and moving it out reduces the conceptual complexity of that code.
Diffstat (limited to 'src/arch/arm/isa/templates/macromem.isa')
-rw-r--r--src/arch/arm/isa/templates/macromem.isa85
1 files changed, 12 insertions, 73 deletions
diff --git a/src/arch/arm/isa/templates/macromem.isa b/src/arch/arm/isa/templates/macromem.isa
index c626bdec8..de5279392 100644
--- a/src/arch/arm/isa/templates/macromem.isa
+++ b/src/arch/arm/isa/templates/macromem.isa
@@ -60,11 +60,11 @@ def template MicroMemDeclare {{
}};
def template MicroMemConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
- RegIndex _ura,
- RegIndex _urb,
- bool _up,
- uint8_t _imm)
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ RegIndex _ura,
+ RegIndex _urb,
+ bool _up,
+ uint8_t _imm)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_ura, _urb, _up, _imm)
{
@@ -89,10 +89,10 @@ def template MicroIntDeclare {{
}};
def template MicroIntConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
- RegIndex _ura,
- RegIndex _urb,
- uint8_t _imm)
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ RegIndex _ura,
+ RegIndex _urb,
+ uint8_t _imm)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_ura, _urb, _imm)
{
@@ -121,74 +121,13 @@ class %(class_name)s : public %(base_class)s
}};
def template MacroMemConstructor {{
-inline %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
+%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
bool index, bool up, bool user, bool writeback, bool load,
uint32_t reglist)
- : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
+ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn,
+ index, up, user, writeback, load, reglist)
{
%(constructor)s;
- uint32_t regs = reglist;
- uint32_t ones = number_of_ones(reglist);
- // Remember that writeback adds a uop
- numMicroops = ones + (writeback ? 1 : 0) + 1;
- microOps = new StaticInstPtr[numMicroops];
- uint32_t addr = 0;
-
- if (!up)
- addr = (ones << 2) - 4;
-
- if (!index)
- addr += 4;
-
- // Add 0 to Rn and stick it in ureg0.
- // This is equivalent to a move.
- microOps[0] = new MicroAddiUop(machInst, INTREG_UREG0, rn, 0);
-
- unsigned reg = 0;
- bool force_user = user & !bits(reglist, 15);
- bool exception_ret = user & bits(reglist, 15);
-
- for (int i = 1; i < ones + 1; i++) {
- // Find the next register.
- while (!bits(regs, reg))
- reg++;
- replaceBits(regs, reg, 0);
-
- unsigned regIdx = reg;
- if (force_user) {
- regIdx = intRegForceUser(regIdx);
- }
-
- if (load) {
- if (reg == INTREG_PC && exception_ret) {
- // This must be the exception return form of ldm.
- microOps[i] =
- new MicroLdrRetUop(machInst, regIdx,
- INTREG_UREG0, up, addr);
- } else {
- microOps[i] =
- new MicroLdrUop(machInst, regIdx, INTREG_UREG0, up, addr);
- }
- } else {
- microOps[i] =
- new MicroStrUop(machInst, regIdx, INTREG_UREG0, up, addr);
- }
-
- if (up)
- addr += 4;
- else
- addr -= 4;
- }
-
- StaticInstPtr &lastUop = microOps[numMicroops - 1];
- if (writeback) {
- if (up) {
- lastUop = new MicroAddiUop(machInst, rn, rn, ones * 4);
- } else {
- lastUop = new MicroSubiUop(machInst, rn, rn, ones * 4);
- }
- }
- lastUop->setLastMicroop();
}
}};