diff options
author | ARM gem5 Developers <none@none> | 2014-01-24 15:29:34 -0600 |
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committer | ARM gem5 Developers <none@none> | 2014-01-24 15:29:34 -0600 |
commit | 612f8f074fa1099cf70faf495d46cc647762a031 (patch) | |
tree | bd1e99c43bf15292395eadd4b7ae3f5c823545c3 /src/arch/arm/isa/templates/macromem.isa | |
parent | f3585c841e964c98911784a187fc4f081a02a0a6 (diff) | |
download | gem5-612f8f074fa1099cf70faf495d46cc647762a031.tar.xz |
arm: Add support for ARMv8 (AArch64 & AArch32)
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.
Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.
Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black
Diffstat (limited to 'src/arch/arm/isa/templates/macromem.isa')
-rw-r--r-- | src/arch/arm/isa/templates/macromem.isa | 126 |
1 files changed, 125 insertions, 1 deletions
diff --git a/src/arch/arm/isa/templates/macromem.isa b/src/arch/arm/isa/templates/macromem.isa index 195204a95..465090660 100644 --- a/src/arch/arm/isa/templates/macromem.isa +++ b/src/arch/arm/isa/templates/macromem.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010 ARM Limited +// Copyright (c) 2010-2013 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -338,6 +338,18 @@ def template MicroIntImmConstructor {{ } }}; +def template MicroIntImmXConstructor {{ + %(class_name)s::%(class_name)s(ExtMachInst machInst, + RegIndex _ura, + RegIndex _urb, + int32_t _imm) + : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, + _ura, _urb, _imm) + { + %(constructor)s; + } +}}; + def template MicroIntRegDeclare {{ class %(class_name)s : public %(base_class)s { @@ -349,6 +361,28 @@ def template MicroIntRegDeclare {{ }; }}; +def template MicroIntXERegConstructor {{ + %(class_name)s::%(class_name)s(ExtMachInst machInst, + RegIndex _ura, RegIndex _urb, RegIndex _urc, + ArmExtendType _type, uint32_t _shiftAmt) + : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, + _ura, _urb, _urc, _type, _shiftAmt) + { + %(constructor)s; + } +}}; + +def template MicroIntXERegDeclare {{ + class %(class_name)s : public %(base_class)s + { + public: + %(class_name)s(ExtMachInst machInst, + RegIndex _ura, RegIndex _urb, RegIndex _urc, + ArmExtendType _type, uint32_t _shiftAmt); + %(BasicExecDeclare)s + }; +}}; + def template MicroIntRegConstructor {{ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _ura, RegIndex _urb, RegIndex _urc, @@ -402,6 +436,96 @@ def template MacroMemConstructor {{ }}; +def template BigFpMemImmDeclare {{ +class %(class_name)s : public %(base_class)s +{ + public: + // Constructor + %(class_name)s(const char *mnemonic, ExtMachInst machInst, + bool load, IntRegIndex dest, IntRegIndex base, int64_t imm); + %(BasicExecPanic)s +}; +}}; + +def template BigFpMemImmConstructor {{ +%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, + bool load, IntRegIndex dest, IntRegIndex base, int64_t imm) + : %(base_class)s(mnemonic, machInst, %(op_class)s, load, dest, base, imm) +{ + %(constructor)s; +} +}}; + +def template BigFpMemRegDeclare {{ +class %(class_name)s : public %(base_class)s +{ + public: + // Constructor + %(class_name)s(const char *mnemonic, ExtMachInst machInst, + bool load, IntRegIndex dest, IntRegIndex base, + IntRegIndex offset, ArmExtendType type, int64_t imm); + %(BasicExecPanic)s +}; +}}; + +def template BigFpMemRegConstructor {{ +%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, + bool load, IntRegIndex dest, IntRegIndex base, + IntRegIndex offset, ArmExtendType type, int64_t imm) + : %(base_class)s(mnemonic, machInst, %(op_class)s, load, dest, base, + offset, type, imm) +{ + %(constructor)s; +} +}}; + +def template BigFpMemLitDeclare {{ +class %(class_name)s : public %(base_class)s +{ + public: + // Constructor + %(class_name)s(const char *mnemonic, ExtMachInst machInst, + IntRegIndex dest, int64_t imm); + %(BasicExecPanic)s +}; +}}; + +def template BigFpMemLitConstructor {{ +%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, + IntRegIndex dest, int64_t imm) + : %(base_class)s(mnemonic, machInst, %(op_class)s, dest, imm) +{ + %(constructor)s; +} +}}; + +def template PairMemDeclare {{ +class %(class_name)s : public %(base_class)s +{ + public: + // Constructor + %(class_name)s(const char *mnemonic, ExtMachInst machInst, + uint32_t size, bool fp, bool load, bool noAlloc, bool signExt, + bool exclusive, bool acrel, uint32_t imm, + AddrMode mode, IntRegIndex rn, IntRegIndex rt, + IntRegIndex rt2); + %(BasicExecPanic)s +}; +}}; + +def template PairMemConstructor {{ +%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, + uint32_t size, bool fp, bool load, bool noAlloc, bool signExt, + bool exclusive, bool acrel, uint32_t imm, AddrMode mode, + IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2) + : %(base_class)s(mnemonic, machInst, %(op_class)s, size, + fp, load, noAlloc, signExt, exclusive, acrel, + imm, mode, rn, rt, rt2) +{ + %(constructor)s; +} +}}; + def template VMemMultDeclare {{ class %(class_name)s : public %(base_class)s { |