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authorAli Saidi <Ali.Saidi@ARM.com>2011-04-04 11:42:28 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2011-04-04 11:42:28 -0500
commita679cd917ac4775979e23594de52f1bca407c08c (patch)
treed48bb74b729d2e11e62e1db9a4fb860b70ddd1b3 /src/arch/arm/isa/templates/mem.isa
parentac650199eeb62bf05fec11a4f2d7666cbd31331c (diff)
downloadgem5-a679cd917ac4775979e23594de52f1bca407c08c.tar.xz
ARM: Cleanup implementation of ITSTATE and put important code in PCState.
Consolidate all code to handle ITSTATE in the PCState object rather than touching a variety of structures/objects.
Diffstat (limited to 'src/arch/arm/isa/templates/mem.isa')
-rw-r--r--src/arch/arm/isa/templates/mem.isa81
1 files changed, 0 insertions, 81 deletions
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index f26ee55e8..43a742242 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -102,11 +102,6 @@ def template SwapExecute {{
xc->setPredicate(false);
}
- if (fault == NoFault && machInst.itstateMask != 0 &&
- (!isMicroop() || isLastMicroop())) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
-
return fault;
}
}};
@@ -135,11 +130,6 @@ def template SwapInitiateAcc {{
xc->setPredicate(false);
}
- if (fault == NoFault && machInst.itstateMask != 0 &&
- (!isMicroop() || isLastMicroop())) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
-
return fault;
}
}};
@@ -166,10 +156,6 @@ def template SwapCompleteAcc {{
}
}
- if (fault == NoFault && machInst.itstateMask != 0) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
-
return fault;
}
}};
@@ -199,11 +185,6 @@ def template LoadExecute {{
xc->setPredicate(false);
}
- if (fault == NoFault && machInst.itstateMask != 0 &&
- (!isMicroop() || isLastMicroop())) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
-
return fault;
}
}};
@@ -238,11 +219,6 @@ def template NeonLoadExecute {{
xc->setPredicate(false);
}
- if (fault == NoFault && machInst.itstateMask != 0 &&
- (!isMicroop() || isLastMicroop())) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
-
return fault;
}
}};
@@ -276,11 +252,6 @@ def template StoreExecute {{
xc->setPredicate(false);
}
- if (fault == NoFault && machInst.itstateMask != 0 &&
- (!isMicroop() || isLastMicroop())) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
-
return fault;
}
}};
@@ -319,11 +290,6 @@ def template NeonStoreExecute {{
xc->setPredicate(false);
}
- if (fault == NoFault && machInst.itstateMask != 0 &&
- (!isMicroop() || isLastMicroop())) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
-
return fault;
}
}};
@@ -363,11 +329,6 @@ def template StoreExExecute {{
xc->setPredicate(false);
}
- if (fault == NoFault && machInst.itstateMask != 0 &&
- (!isMicroop() || isLastMicroop())) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
-
return fault;
}
}};
@@ -396,10 +357,6 @@ def template StoreExInitiateAcc {{
} else {
xc->setPredicate(false);
}
- if (fault == NoFault && machInst.itstateMask != 0 &&
- (!isMicroop() || isLastMicroop())) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
return fault;
}
@@ -430,11 +387,6 @@ def template StoreInitiateAcc {{
xc->setPredicate(false);
}
- if (fault == NoFault && machInst.itstateMask != 0 &&
- (!isMicroop() || isLastMicroop())) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
-
return fault;
}
}};
@@ -467,11 +419,6 @@ def template NeonStoreInitiateAcc {{
xc->setPredicate(false);
}
- if (fault == NoFault && machInst.itstateMask != 0 &&
- (!isMicroop() || isLastMicroop())) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
-
return fault;
}
}};
@@ -494,10 +441,6 @@ def template LoadInitiateAcc {{
}
} else {
xc->setPredicate(false);
- if (fault == NoFault && machInst.itstateMask != 0 &&
- (!isMicroop() || isLastMicroop())) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
}
return fault;
@@ -523,10 +466,6 @@ def template NeonLoadInitiateAcc {{
}
} else {
xc->setPredicate(false);
- if (fault == NoFault && machInst.itstateMask != 0 &&
- (!isMicroop() || isLastMicroop())) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
}
return fault;
@@ -557,10 +496,6 @@ def template LoadCompleteAcc {{
}
}
- if (fault == NoFault && machInst.itstateMask != 0) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
-
return fault;
}
}};
@@ -591,10 +526,6 @@ def template NeonLoadCompleteAcc {{
}
}
- if (fault == NoFault && machInst.itstateMask != 0) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
-
return fault;
}
}};
@@ -604,10 +535,6 @@ def template StoreCompleteAcc {{
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- if (machInst.itstateMask != 0) {
- warn_once("Complete acc isn't called on normal stores in O3.");
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
return NoFault;
}
}};
@@ -618,10 +545,6 @@ def template NeonStoreCompleteAcc {{
PacketPtr pkt, %(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- if (machInst.itstateMask != 0) {
- warn_once("Complete acc isn't called on normal stores in O3.");
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
return NoFault;
}
}};
@@ -646,10 +569,6 @@ def template StoreExCompleteAcc {{
}
}
- if (fault == NoFault && machInst.itstateMask != 0) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
-
return fault;
}
}};