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authorARM gem5 Developers <none@none>2014-01-24 15:29:34 -0600
committerARM gem5 Developers <none@none>2014-01-24 15:29:34 -0600
commit612f8f074fa1099cf70faf495d46cc647762a031 (patch)
treebd1e99c43bf15292395eadd4b7ae3f5c823545c3 /src/arch/arm/isa/templates/mem.isa
parentf3585c841e964c98911784a187fc4f081a02a0a6 (diff)
downloadgem5-612f8f074fa1099cf70faf495d46cc647762a031.tar.xz
arm: Add support for ARMv8 (AArch64 & AArch32)
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
Diffstat (limited to 'src/arch/arm/isa/templates/mem.isa')
-rw-r--r--src/arch/arm/isa/templates/mem.isa22
1 files changed, 21 insertions, 1 deletions
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index 871378f3f..7682c277d 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2010 ARM Limited
+// Copyright (c) 2010, 2012 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -697,6 +697,11 @@ def template LoadStoreImmDeclare {{
%(InitiateAccDeclare)s
%(CompleteAccDeclare)s
+
+ virtual void
+ annotateFault(ArmFault *fault) {
+ %(fa_code)s
+ }
};
}};
@@ -763,6 +768,11 @@ def template StoreRegDeclare {{
%(InitiateAccDeclare)s
%(CompleteAccDeclare)s
+
+ virtual void
+ annotateFault(ArmFault *fault) {
+ %(fa_code)s
+ }
};
}};
@@ -808,6 +818,11 @@ def template LoadRegDeclare {{
%(InitiateAccDeclare)s
%(CompleteAccDeclare)s
+
+ virtual void
+ annotateFault(ArmFault *fault) {
+ %(fa_code)s
+ }
};
}};
@@ -828,6 +843,11 @@ def template LoadImmDeclare {{
%(InitiateAccDeclare)s
%(CompleteAccDeclare)s
+
+ virtual void
+ annotateFault(ArmFault *fault) {
+ %(fa_code)s
+ }
};
}};