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author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:28 -0500 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:28 -0500 |
commit | a679cd917ac4775979e23594de52f1bca407c08c (patch) | |
tree | d48bb74b729d2e11e62e1db9a4fb860b70ddd1b3 /src/arch/arm/isa/templates/misc.isa | |
parent | ac650199eeb62bf05fec11a4f2d7666cbd31331c (diff) | |
download | gem5-a679cd917ac4775979e23594de52f1bca407c08c.tar.xz |
ARM: Cleanup implementation of ITSTATE and put important code in PCState.
Consolidate all code to handle ITSTATE in the PCState object rather than
touching a variety of structures/objects.
Diffstat (limited to 'src/arch/arm/isa/templates/misc.isa')
-rw-r--r-- | src/arch/arm/isa/templates/misc.isa | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa index 0347869f8..694dc46da 100644 --- a/src/arch/arm/isa/templates/misc.isa +++ b/src/arch/arm/isa/templates/misc.isa @@ -438,9 +438,6 @@ def template ClrexInitiateAcc {{ } } else { xc->setPredicate(false); - if (fault == NoFault && machInst.itstateMask != 0) { - xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); - } } return fault; @@ -452,10 +449,6 @@ def template ClrexCompleteAcc {{ %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { - if (machInst.itstateMask != 0) { - xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); - } - return NoFault; } }}; |