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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:08 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:08 -0500
commitb1158e493843066acdba153c89573273f5d0fd73 (patch)
tree1ec9ac7d5355ec1ed6a3335cad8996449fb39e82 /src/arch/arm/isa/templates/misc.isa
parent504ac6518bea90d614c2d2394fa3881f8557d798 (diff)
downloadgem5-b1158e493843066acdba153c89573273f5d0fd73.tar.xz
ARM: Add a register, immediate, immediate to register base for [su]bfx.
Diffstat (limited to 'src/arch/arm/isa/templates/misc.isa')
-rw-r--r--src/arch/arm/isa/templates/misc.isa26
1 files changed, 26 insertions, 0 deletions
diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
index 7a9a35ec9..83d165365 100644
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -196,6 +196,32 @@ def template RegRegRegOpConstructor {{
}
}};
+def template RegRegImmImmOpDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+ protected:
+ public:
+ // Constructor
+ %(class_name)s(ExtMachInst machInst,
+ IntRegIndex _dest, IntRegIndex _op1,
+ uint32_t _imm1, uint32_t _imm2);
+ %(BasicExecDeclare)s
+};
+}};
+
+def template RegRegImmImmOpConstructor {{
+ inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ IntRegIndex _dest,
+ IntRegIndex _op1,
+ uint32_t _imm1,
+ uint32_t _imm2)
+ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+ _dest, _op1, _imm1, _imm2)
+ {
+ %(constructor)s;
+ }
+}};
+
def template RegImmRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{