diff options
author | Gabe Black <gabeblack@google.com> | 2017-11-04 03:45:23 -0700 |
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committer | Gabe Black <gabeblack@google.com> | 2017-11-07 01:31:24 +0000 |
commit | 344911b885114b8401482679202aaee89fa8b29b (patch) | |
tree | 395424b6f248c24977462489c8c1e3c1e97e7c34 /src/arch/arm/isa/templates/neon64.isa | |
parent | 7e02ab1dc622081a30e5b8bec3a944bd1fc7fca6 (diff) | |
download | gem5-344911b885114b8401482679202aaee89fa8b29b.tar.xz |
alpha,arm,mips,power,riscv,sparc,x86: Merge exec decl templates.
In the ISA instruction definitions, some classes were declared with
execute, etc., functions outside of the main template because they
had CPU specific signatures and would need to be duplicated with
each CPU plugged into them. Now that the instructions always just
use an ExecContext, there's no reason for those templates to be
separate. This change folds those templates together.
Change-Id: I13bda247d3d1cc07c0ea06968e48aa5b4aace7fa
Reviewed-on: https://gem5-review.googlesource.com/5401
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/templates/neon64.isa')
-rw-r--r-- | src/arch/arm/isa/templates/neon64.isa | 24 |
1 files changed, 11 insertions, 13 deletions
diff --git a/src/arch/arm/isa/templates/neon64.isa b/src/arch/arm/isa/templates/neon64.isa index f11ee91d4..153933611 100644 --- a/src/arch/arm/isa/templates/neon64.isa +++ b/src/arch/arm/isa/templates/neon64.isa @@ -58,7 +58,7 @@ class %(class_name)s : public %(base_class)s %(constructor)s; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -79,7 +79,7 @@ class %(class_name)s : public %(base_class)s %(constructor)s; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -99,7 +99,7 @@ class %(class_name)s : public %(base_class)s %(constructor)s; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -119,7 +119,7 @@ class %(class_name)s : public %(base_class)s %(constructor)s; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -140,7 +140,7 @@ class %(class_name)s : public %(base_class)s %(constructor)s; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -160,7 +160,7 @@ class %(class_name)s : public %(base_class)s %(constructor)s; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -267,9 +267,9 @@ def template MicroNeonMemDeclare64 {{ %(constructor)s; } - %(BasicExecDeclare)s - %(InitiateAccDeclare)s - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }; }}; @@ -420,7 +420,6 @@ def template VMemMultDeclare64 {{ %(class_name)s(ExtMachInst machInst, RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs, bool wb); - %(BasicExecPanic)s }; }}; @@ -433,7 +432,6 @@ def template VMemSingleDeclare64 {{ RegIndex rm, uint8_t eSize, uint8_t dataSize, uint8_t numStructElems, uint8_t index, bool wb, bool replicate = false); - %(BasicExecPanic)s }; }}; @@ -479,7 +477,7 @@ def template MicroNeonMixDeclare64 {{ %(constructor)s; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -498,7 +496,7 @@ def template MicroNeonMixLaneDeclare64 {{ %(constructor)s; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; |