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author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:16 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:16 -0500 |
commit | 05bd3eb4ec3d9fea3dbc46112a47459085d3011c (patch) | |
tree | 58d50fab58de1e9165bfc28986913811b26b9568 /src/arch/arm/isa/templates/pred.isa | |
parent | b93ceef5381b7c84b6887b5299ae81ff48ef45c9 (diff) | |
download | gem5-05bd3eb4ec3d9fea3dbc46112a47459085d3011c.tar.xz |
ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR.
Diffstat (limited to 'src/arch/arm/isa/templates/pred.isa')
-rw-r--r-- | src/arch/arm/isa/templates/pred.isa | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa index 15d34da19..c8f30ddf0 100644 --- a/src/arch/arm/isa/templates/pred.isa +++ b/src/arch/arm/isa/templates/pred.isa @@ -46,7 +46,11 @@ // let {{ - predicateTest = 'testPredicate(CondCodes, condCode)' + predicateTest = ''' + testPredicate(CondCodes, machInst.itstateMask ? + (ConditionCode)(uint8_t)machInst.itstateCond : + condCode) + ''' }}; def template DataImmDeclare {{ @@ -143,6 +147,10 @@ def template PredOpExecute {{ } } + if (fault == NoFault && machInst.itstateMask != 0) { + xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); + } + return fault; } }}; |