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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:17 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:17 -0500 |
| commit | 358fdc2a40e8a455f508532b47e55f3252053805 (patch) | |
| tree | 4641a564de6d0ce42a372be77e35cde55e2c177c /src/arch/arm/isa/templates/pred.isa | |
| parent | 596cbe19d4591b900acc022ff5a38fc7ee9a5df7 (diff) | |
| download | gem5-358fdc2a40e8a455f508532b47e55f3252053805.tar.xz | |
ARM: Decode to specialized conditional/unconditional versions of instructions.
This is to avoid condition code based dependences from effectively serializing
instructions when the instruction doesn't actually use them.
Diffstat (limited to 'src/arch/arm/isa/templates/pred.isa')
| -rw-r--r-- | src/arch/arm/isa/templates/pred.isa | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa index c8f30ddf0..7a5b92760 100644 --- a/src/arch/arm/isa/templates/pred.isa +++ b/src/arch/arm/isa/templates/pred.isa @@ -46,11 +46,8 @@ // let {{ - predicateTest = ''' - testPredicate(CondCodes, machInst.itstateMask ? - (ConditionCode)(uint8_t)machInst.itstateCond : - condCode) - ''' + predicateTest = 'testPredicate(OptCondCodes, condCode)' + condPredicateTest = 'testPredicate(CondCodes, condCode)' }}; def template DataImmDeclare {{ |