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author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-09-25 11:49:40 -0500 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-09-25 11:49:40 -0500 |
commit | 04ca96427c1c910f0bddb2403dec9ea517f3869b (patch) | |
tree | 9543fed87f3a76b07a7074ab9408a2823f97873c /src/arch/arm/isa/templates/pred.isa | |
parent | 17aa2b0f1be705b0f33ff486509b6962cf1a541d (diff) | |
download | gem5-04ca96427c1c910f0bddb2403dec9ea517f3869b.tar.xz |
ARM: Predict target of more instructions that modify PC.
Diffstat (limited to 'src/arch/arm/isa/templates/pred.isa')
-rw-r--r-- | src/arch/arm/isa/templates/pred.isa | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa index 88e8fecd1..918029cc2 100644 --- a/src/arch/arm/isa/templates/pred.isa +++ b/src/arch/arm/isa/templates/pred.isa @@ -76,6 +76,15 @@ def template DataImmConstructor {{ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; } } + + if (%(is_branch)s){ + flags[IsControl] = true; + flags[IsIndirectControl] = true; + if (condCode == COND_AL || condCode == COND_UC) + flags[IsUncondControl] = true; + else + flags[IsCondControl] = true; + } } }}; |