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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:27 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:27 -0500 |
| commit | be096f91b94ded36f43dd7d547a5671f99a264b1 (patch) | |
| tree | 85442361558d1123c441538a173dabc9a3fa0a6c /src/arch/arm/isa/templates/pred.isa | |
| parent | 55920a5ca73ded58762f1b7ae25c8cfe8c9e407d (diff) | |
| download | gem5-be096f91b94ded36f43dd7d547a5671f99a264b1.tar.xz | |
ARM: Tag appropriate instructions as IsReturn
Diffstat (limited to 'src/arch/arm/isa/templates/pred.isa')
| -rw-r--r-- | src/arch/arm/isa/templates/pred.isa | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa index 2a4bd9dab..95c7c8e1b 100644 --- a/src/arch/arm/isa/templates/pred.isa +++ b/src/arch/arm/isa/templates/pred.isa @@ -107,6 +107,19 @@ def template DataRegConstructor {{ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; } } + + if (%(is_branch)s){ + flags[IsControl] = true; + flags[IsIndirectControl] = true; + if (condCode == COND_AL || condCode == COND_UC) + flags[IsCondControl] = true; + else + flags[IsUncondControl] = true; + } + + if (%(is_ras_pop)s) { + flags[IsReturn] = true; + } } }}; |