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authorGene Wu <Gene.Wu@arm.com>2010-08-23 11:18:41 -0500
committerGene Wu <Gene.Wu@arm.com>2010-08-23 11:18:41 -0500
commit1fd104fc35ed5a1fa01e5709aba0dec58a5db6f5 (patch)
tree57a5455206e3ce6b4332735bd9610342257ff8af /src/arch/arm/isa/templates
parent9db2ab8a62397e5d277760c86db1ef3db63f7342 (diff)
downloadgem5-1fd104fc35ed5a1fa01e5709aba0dec58a5db6f5.tar.xz
ARM: Don't write tracedata on writes, it might have been freed already.
Diffstat (limited to 'src/arch/arm/isa/templates')
-rw-r--r--src/arch/arm/isa/templates/mem.isa4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index 5431777b2..84cd1dd8f 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -200,7 +200,6 @@ def template StoreExecute {{
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, NULL);
- if (traceData) { traceData->setData(Mem); }
}
if (fault == NoFault) {
@@ -240,7 +239,6 @@ def template StoreExExecute {{
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, &writeResult);
- if (traceData) { traceData->setData(Mem); }
}
if (fault == NoFault) {
@@ -282,7 +280,6 @@ def template StoreExInitiateAcc {{
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, NULL);
- if (traceData) { traceData->setData(Mem); }
}
// Need to write back any potential address register update
@@ -321,7 +318,6 @@ def template StoreInitiateAcc {{
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, NULL);
- if (traceData) { traceData->setData(Mem); }
}
// Need to write back any potential address register update