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authorGabe Black <gblack@eecs.umich.edu>2010-10-22 00:23:19 -0700
committerGabe Black <gblack@eecs.umich.edu>2010-10-22 00:23:19 -0700
commit29676286c8b52014c44f5001ff2d039881189030 (patch)
tree60a674e87d97659ccb822ce9277f2cb0abcd6582 /src/arch/arm/isa/templates
parentbc49381287698297446da3e6f7b43b8ef4f43b27 (diff)
downloadgem5-29676286c8b52014c44f5001ff2d039881189030.tar.xz
ISA: Simplify various implementations of completeAcc.
Diffstat (limited to 'src/arch/arm/isa/templates')
-rw-r--r--src/arch/arm/isa/templates/mem.isa36
-rw-r--r--src/arch/arm/isa/templates/misc.isa10
2 files changed, 8 insertions, 38 deletions
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index ced7a0037..29ef8d007 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -595,23 +595,11 @@ def template StoreCompleteAcc {{
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- Fault fault = NoFault;
-
- %(op_decl)s;
- %(op_rd)s;
-
- if (%(predicate_test)s)
- {
- if (fault == NoFault) {
- %(op_wb)s;
- }
- }
-
- if (fault == NoFault && machInst.itstateMask != 0) {
+ if (machInst.itstateMask != 0) {
+ warn_once("Complete acc isn't called on normal stores in O3.");
xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
}
-
- return fault;
+ return NoFault;
}
}};
@@ -621,23 +609,11 @@ def template NeonStoreCompleteAcc {{
PacketPtr pkt, %(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- Fault fault = NoFault;
-
- %(op_decl)s;
- %(op_rd)s;
-
- if (%(predicate_test)s)
- {
- if (fault == NoFault) {
- %(op_wb)s;
- }
- }
-
- if (fault == NoFault && machInst.itstateMask != 0) {
+ if (machInst.itstateMask != 0) {
+ warn_once("Complete acc isn't called on normal stores in O3.");
xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
}
-
- return fault;
+ return NoFault;
}
}};
diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
index f8dac05f8..915dea9b0 100644
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -387,17 +387,11 @@ def template ClrexCompleteAcc {{
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- Fault fault = NoFault;
-
- %(op_decl)s;
- %(op_rd)s;
-
-
- if (fault == NoFault && machInst.itstateMask != 0) {
+ if (machInst.itstateMask != 0) {
xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
}
- return fault;
+ return NoFault;
}
}};