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authorGiacomo Travaglini <giacomo.travaglini@arm.com>2017-11-10 15:35:26 +0000
committerGiacomo Travaglini <giacomo.travaglini@arm.com>2017-11-21 14:25:56 +0000
commit2a2c66c16c659af4c3588b6c1646d55c66ad53fe (patch)
tree633dd84e28b040febbe2fd2efc7cd0a62dc7f60d /src/arch/arm/isa/templates
parentd3ec34201c14d551e864372a89ccddb1c255e77a (diff)
downloadgem5-2a2c66c16c659af4c3588b6c1646d55c66ad53fe.tar.xz
arch-arm: Fix MSR/MRS disassemble
This patch is fixing the Aarch64 MSR/MRS disassemble, which was previously printing unexisting integer registers as source/destination operands rather than the system register name Change-Id: Iac9d5f2f2fea85abd9a398320ef7aa4844d43c0e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5861 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/templates')
-rw-r--r--src/arch/arm/isa/templates/misc64.isa49
1 files changed, 48 insertions, 1 deletions
diff --git a/src/arch/arm/isa/templates/misc64.isa b/src/arch/arm/isa/templates/misc64.isa
index 842997902..48d5c6426 100644
--- a/src/arch/arm/isa/templates/misc64.isa
+++ b/src/arch/arm/isa/templates/misc64.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2011 ARM Limited
+// Copyright (c) 2011,2017 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -89,3 +89,50 @@ def template RegRegRegImmOp64Constructor {{
}
}};
+def template MiscRegRegOp64Declare {{
+class %(class_name)s : public %(base_class)s
+{
+ public:
+ // Constructor
+ %(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
+ IntRegIndex _op1, uint64_t _imm);
+
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+};
+}};
+
+def template MiscRegRegOp64Constructor {{
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ MiscRegIndex _dest,
+ IntRegIndex _op1,
+ uint64_t _imm)
+ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+ _dest, _op1, _imm)
+ {
+ %(constructor)s;
+ }
+}};
+
+def template RegMiscRegOp64Declare {{
+class %(class_name)s : public %(base_class)s
+{
+ public:
+ // Constructor
+ %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
+ MiscRegIndex _op1, uint64_t _imm);
+
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+};
+}};
+
+def template RegMiscRegOp64Constructor {{
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ IntRegIndex _dest,
+ MiscRegIndex _op1,
+ uint64_t _imm)
+ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+ _dest, _op1, _imm)
+ {
+ %(constructor)s;
+ }
+}};