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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-09-25 11:49:40 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-09-25 11:49:40 -0500 |
| commit | 04ca96427c1c910f0bddb2403dec9ea517f3869b (patch) | |
| tree | 9543fed87f3a76b07a7074ab9408a2823f97873c /src/arch/arm/isa/templates | |
| parent | 17aa2b0f1be705b0f33ff486509b6962cf1a541d (diff) | |
| download | gem5-04ca96427c1c910f0bddb2403dec9ea517f3869b.tar.xz | |
ARM: Predict target of more instructions that modify PC.
Diffstat (limited to 'src/arch/arm/isa/templates')
| -rw-r--r-- | src/arch/arm/isa/templates/mem.isa | 18 | ||||
| -rw-r--r-- | src/arch/arm/isa/templates/pred.isa | 9 |
2 files changed, 27 insertions, 0 deletions
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa index a4a740f89..2ccda65e1 100644 --- a/src/arch/arm/isa/templates/mem.isa +++ b/src/arch/arm/isa/templates/mem.isa @@ -1155,6 +1155,15 @@ def template LoadRegConstructor {{ uops[1]->setLastMicroop(); } +#else + if (_dest == INTREG_PC) { + flags[IsControl] = true; + flags[IsIndirectControl] = true; + if (conditional) + flags[IsCondControl] = true; + else + flags[IsUncondControl] = true; + } #endif } }}; @@ -1198,6 +1207,15 @@ def template LoadImmConstructor {{ uops[1] = new %(wb_decl)s; uops[1]->setLastMicroop(); } +#else + if (_dest == INTREG_PC) { + flags[IsControl] = true; + flags[IsIndirectControl] = true; + if (conditional) + flags[IsCondControl] = true; + else + flags[IsUncondControl] = true; + } #endif } }}; diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa index 88e8fecd1..918029cc2 100644 --- a/src/arch/arm/isa/templates/pred.isa +++ b/src/arch/arm/isa/templates/pred.isa @@ -76,6 +76,15 @@ def template DataImmConstructor {{ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; } } + + if (%(is_branch)s){ + flags[IsControl] = true; + flags[IsIndirectControl] = true; + if (condCode == COND_AL || condCode == COND_UC) + flags[IsUncondControl] = true; + else + flags[IsCondControl] = true; + } } }}; |